time_mux.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module time_mux(
				TimeSet_EN,
				hour1,hour0,
				minute1,minute0,
				second1,second0,
				hour_set1,hour_set0,
				minute_set1,minute_set0,
				second_set1,second_set0,
				hour_1,hour_0,
				minute_1,minute_0,
				second_1,second_0
				);
output [3:0] hour_1,hour_0;
output [3:0] minute_1,minute_0;
output [3:0] second_1,second_0;
input  TimeSet_EN;
input  [3:0] hour1,hour0;
input  [3:0] minute1,minute0;
input  [3:0] second1,second0;
input  [3:0] hour_set1,hour_set0;
input  [3:0] minute_set1,minute_set0;
input  [3:0] second_set1,second_set0;

reg [3:0] hour_1,hour_0;
reg [3:0] minute_1,minute_0;
reg [3:0] second_1,second_0;

always @(TimeSet_EN,
         hour1,hour0,
		 minute1,minute0,
		 second1,second0,
		 hour_set1,hour_set0,
		 minute_set1,minute_set0,
		 second_set1,second_set0)
begin
  if(TimeSet_EN == 1'b1)
    begin
      hour_1   <= hour_set1;
      hour_0   <= hour_set0;
      minute_1 <= minute_set1;
      minute_0 <= minute_set0;
      second_1 <= second_set1;
      second_0 <= second_set0;
      
    end
  else
    begin
      hour_1   <= hour1;
      hour_0   <= hour0;
      minute_1 <= minute1;
      minute_0 <= minute0;
      second_1 <= second1;
      second_0 <= second0;
    end
end
endmodule