main.fit.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 23:19:06 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : Stratix
Met timing requirements : N/A
Total logic elements : 489 / 10,570 ( 4 % )
Total pins : 18 / 336 ( 5 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Final