main.sim.vwf

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· VWF 代码 · 共 1,015 行 · 第 1/2 页

VWF
1,015 行
字号
12
		LEVEL 1 FOR 46.066;
		LEVEL 0 FOR 0.436;
		LEVEL 1 FOR 0.197;
		LEVEL 0 FOR 0.708;
		LEVEL 1 FOR 2.451;
		LEVEL 0 FOR 0.486;
		LEVEL 1 FOR 8.268;
		LEVEL 0 FOR 1.388;
		LEVEL 1 FOR 24.4;
		LEVEL 0 FOR 13.613;
		LEVEL 1 FOR 1.221;
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		LEVEL 1 FOR 145.507;
		LEVEL 0 FOR 0.152;
		LEVEL 1 FOR 0.999;
		LEVEL 0 FOR 1.064;
		LEVEL 1 FOR 31.074;
	}
}

TRANSITION_LIST("disp_data[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 61.204;
		LEVEL 1 FOR 23.018;
		LEVEL 0 FOR 1.047;
		LEVEL 1 FOR 45.818;
		LEVEL 0 FOR 0.436;
		LEVEL 1 FOR 12.699;
		LEVEL 0 FOR 1.047;
		LEVEL 1 FOR 25.76;
		LEVEL 0 FOR 10.9;
		LEVEL 1 FOR 33.798;
		LEVEL 0 FOR 7.381;
		LEVEL 1 FOR 0.771;
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		LEVEL 1 FOR 147.629;
		LEVEL 0 FOR 1.125;
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		LEVEL 0 FOR 0.152;
		LEVEL 1 FOR 0.998;
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		LEVEL 0 FOR 1.047;
		LEVEL 1 FOR 45.818;
		LEVEL 0 FOR 0.436;
		LEVEL 1 FOR 3.356;
		LEVEL 0 FOR 0.486;
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		LEVEL 0 FOR 1.047;
		LEVEL 1 FOR 24.152;
		LEVEL 0 FOR 0.893;
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		LEVEL 0 FOR 12.873;
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		LEVEL 1 FOR 105.374;
		LEVEL 0 FOR 0.152;
		LEVEL 1 FOR 0.998;
		LEVEL 0 FOR 0.926;
		LEVEL 1 FOR 31.212;
	}
}

TRANSITION_LIST("disp_data[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 61.233;
		LEVEL 0 FOR 21.842;
		LEVEL 1 FOR 1.144;
		LEVEL 0 FOR 0.785;
		LEVEL 1 FOR 0.262;
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		LEVEL 1 FOR 0.708;
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		LEVEL 1 FOR 1.144;
		LEVEL 0 FOR 0.785;
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		LEVEL 0 FOR 25.76;
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		LEVEL 1 FOR 1.144;
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		LEVEL 1 FOR 41.02;
		LEVEL 0 FOR 146.563;
		LEVEL 1 FOR 1.066;
		LEVEL 0 FOR 0.863;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 247.994;
		LEVEL 1 FOR 1.563;
		LEVEL 0 FOR 0.4;
		LEVEL 1 FOR 0.279;
		LEVEL 0 FOR 3.619;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 5.936;
		LEVEL 1 FOR 0.426;
		LEVEL 0 FOR 8.946;
		LEVEL 1 FOR 1.144;
		LEVEL 0 FOR 0.785;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 46.456;
		LEVEL 1 FOR 0.708;
		LEVEL 0 FOR 10.645;
		LEVEL 1 FOR 1.144;
		LEVEL 0 FOR 0.785;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 25.04;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 1.051;
		LEVEL 1 FOR 42.428;
		LEVEL 0 FOR 6.959;
		LEVEL 1 FOR 40.329;
		LEVEL 0 FOR 106.262;
		LEVEL 1 FOR 0.262;
		LEVEL 0 FOR 32.141;
	}
}

TRANSITION_LIST("disp_select[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 59.465;
		LEVEL 0 FOR 8.896;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 25.399;
		LEVEL 1 FOR 46.106;
		LEVEL 0 FOR 148.693;
		LEVEL 1 FOR 48.969;
		LEVEL 0 FOR 260.833;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 261.639;
	}
}

TRANSITION_LIST("disp_select[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 60.144;
		LEVEL 0 FOR 17.696;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 61.505;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 148.879;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 0.367;
		LEVEL 1 FOR 0.083;
		LEVEL 0 FOR 149.764;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 19.402;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 252.16;
	}
}

TRANSITION_LIST("disp_select[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 60.373;
		LEVEL 0 FOR 27.83;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 101.505;
		LEVEL 1 FOR 98.788;
		LEVEL 0 FOR 99.982;
		LEVEL 1 FOR 0.342;
		LEVEL 0 FOR 0.083;
		LEVEL 1 FOR 0.402;
		LEVEL 0 FOR 199.373;
		LEVEL 1 FOR 9.525;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 2.464;
		LEVEL 1 FOR 0.348;
		LEVEL 0 FOR 2.587;
		LEVEL 1 FOR 46.106;
		LEVEL 0 FOR 150.158;
		LEVEL 1 FOR 40.134;
	}
}

TRANSITION_LIST("disp_select[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 60.641;
		LEVEL 0 FOR 37.851;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 0.339;
		LEVEL 0 FOR 0.113;
		LEVEL 1 FOR 4.947;
		LEVEL 0 FOR 534.601;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 0.339;
		LEVEL 0 FOR 0.113;
		LEVEL 1 FOR 4.947;
		LEVEL 0 FOR 46.106;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 140.003;
	}
}

TRANSITION_LIST("disp_select[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 60.634;
		LEVEL 0 FOR 47.74;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 590.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 141.505;
		LEVEL 1 FOR 98.785;
		LEVEL 0 FOR 41.336;
	}
}

TRANSITION_LIST("disp_select[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 60.461;
		LEVEL 0 FOR 57.732;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 590.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 271.807;
	}
}

TRANSITION_LIST("SW1")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 25;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
	}
}

TRANSITION_LIST("SW2")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 50;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("SW3")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
	}
}

DISPLAY_LINE
{
	CHANNEL = "Clock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_data[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 0;
	CHILDREN = 10, 11, 12, 13, 14, 15;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "disp_select[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 9;
}

DISPLAY_LINE
{
	CHANNEL = "SW1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SW2";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SW3";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "alarm";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 10050;
	MASTER = TRUE;
}
;
12

main.sim.vwf - 源码说明

本页面展示了「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」中的 main.sim.vwf 源码文件，采用 VWF 编程语言编写，共 1,015 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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