main.fit.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 23:18:29 2006 " "Info: Processing started: Sat Jul 15 23:18:29 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off main -c main " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off main -c main" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "main EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design main" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F484C5 " "Info: Device EP1S20F484C5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "18 18 " "Info: No exact pin location assignment(s) for 18 pins of 18 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "alarm " "Info: Pin alarm not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { -32 1280 1456 -16 "alarm" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "alarm" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { alarm } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { alarm } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[6\] " "Info: Pin disp_data\[6\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[6\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[6] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[5\] " "Info: Pin disp_data\[5\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[5\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[5] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[4\] " "Info: Pin disp_data\[4\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[4\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[4] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[3\] " "Info: Pin disp_data\[3\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[3\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[3] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[2\] " "Info: Pin disp_data\[2\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[2\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[2] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[1\] " "Info: Pin disp_data\[1\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[1\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[1] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_data\[0\] " "Info: Pin disp_data\[0\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_data\[0\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data[0] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_data[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[5\] " "Info: Pin disp_select\[5\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[5\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[5] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[4\] " "Info: Pin disp_select\[4\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[4\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[4] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[3\] " "Info: Pin disp_select\[3\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[3\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[3] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[2\] " "Info: Pin disp_select\[2\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[2\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[2] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[1\] " "Info: Pin disp_select\[1\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[1\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[1] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "disp_select\[0\] " "Info: Pin disp_select\[0\] not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 480 1280 1456 496 "disp_select\[5..0\]" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "disp_select\[0\]" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_select[0] } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { disp_select[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SW2 " "Info: Pin SW2 not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { SW2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SW3 " "Info: Pin SW3 not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW3" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW3 } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { SW3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SW1 " "Info: Pin SW1 not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 408 -40 128 424 "SW1" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { SW1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Clock " "Info: Pin Clock not assigned to an exact location on the device" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.fld" "" "" { Clock } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SW2 Global clock in PIN L2 " "Info: Automatically promoted signal \"SW2\" to use Global clock in PIN L2" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Clock Global clock in PIN L3 " "Info: Automatically promoted some destinations of signal \"Clock\" to use Global clock in PIN L3" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "time_disp_select:inst6\|clk~22 " "Info: Destination \"time_disp_select:inst6\|clk~22\" may be non-global or may not use global clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SW3 Global clock in PIN M2 " "Info: Automatically promoted signal \"SW3\" to use Global clock in PIN M2" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SW1 Global clock in PIN M3 " "Info: Automatically promoted signal \"SW1\" to use Global clock in PIN M3" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 408 -40 128 424 "SW1" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fdiv:inst5\|f200hz Global clock " "Info: Automatically promoted some destinations of signal \"fdiv:inst5\|f200hz\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "time_disp_select:inst6\|clk~21 " "Info: Destination \"time_disp_select:inst6\|clk~21\" may be non-global or may not use global clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO Global clock " "Info: Automatically promoted signal \"time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO\" to use Global clock" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0}