main.tan.qmsg

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· QMSG 代码 · 共 23 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[1\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[2\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[2\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[3\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[3\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[4\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[4\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[5\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[5\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}