main.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 23:19:21 2006 " "Info: Processing started: Sat Jul 15 23:19:21 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off main -c main --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[2\] " "Warning: Node \"disp_data_mux:inst8\|Data\[2\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[3\] " "Warning: Node \"disp_data_mux:inst8\|Data\[3\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[0\] " "Warning: Node \"disp_data_mux:inst8\|Data\[0\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[1\] " "Warning: Node \"disp_data_mux:inst8\|Data\[1\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[1\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[1\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[0\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[0\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[2\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[2\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|clk " "Warning: Node \"time_disp_select:inst6\|clk\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[5\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[5\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[4\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[4\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[3\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[3\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[2\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[2\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[1\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[1\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[0\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[0\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[0\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[0\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}