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基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 23:18:27 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : Stratix
Met timing requirements : N/A
Total logic elements : 501
Total pins : 18
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0