disp_data_mux.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module disp_data_mux(
					  Timepiece_EN,
					  TimeSet_EN,
					  Stopwatch_EN,
					  time_disp_select,
					  Alarmclock_EN,
					  alarmclock_disp_select,
					  hour1,hour0,
					  minute1,minute0,
					  second1,second0,
					  Date_EN,
					  DateSet_EN,
					  date_disp_select,
					  month1,month0,
					  day1,day0,
					  disp_select,
					  disp_data					  
					  );

output [5:0] disp_select;
output [6:0] disp_data;

input  Timepiece_EN,TimeSet_EN,Stopwatch_EN;
input  [5:0] time_disp_select;

input  Alarmclock_EN;
input  [5:0] alarmclock_disp_select;

input  [3:0] hour1,hour0,minute1,minute0,second1,second0;

input  Date_EN,DateSet_EN;
input  [5:0] date_disp_select;
input  [3:0] month1,month0,day1,day0;

reg [5:0] disp_select;
reg [6:0] disp_data;

reg [3:0] Data;

always @(Timepiece_EN,
		 TimeSet_EN,
		 Stopwatch_EN,
		 time_disp_select,
		 Alarmclock_EN,
		 alarmclock_disp_select,
		 hour1,hour0,
		 minute1,minute0,
		 second1,second0,
		 Date_EN,
		 DateSet_EN,
		 date_disp_select,
		 month1,month0,
		 day1,day0,
		 disp_select)
begin
  //时钟，秒表显示
  if((Timepiece_EN || TimeSet_EN || Stopwatch_EN) == 1'b1)
  begin
    disp_select <= time_disp_select;
    case(time_disp_select)
      6'b100000: Data <= hour1;
      6'b010000: Data <= hour0;
      6'b001000: Data <= minute1;
      6'b000100: Data <= minute0;
      6'b000010: Data <= second1;
      6'b000001: Data <= second0;
      default:   Data <= 4'b0;
    endcase
  end
  //闹钟设置显示
  else if(Alarmclock_EN == 1'b1)
  begin
    disp_select <= alarmclock_disp_select;
    case(alarmclock_disp_select)
      6'b100000: Data <= hour1;
      6'b010000: Data <= hour0;
      6'b001000: Data <= minute1;
      6'b000100: Data <= minute0;
      6'b000010: Data <= second1;
      6'b000001: Data <= second0;
      default:   Data <= 4'b0;
    endcase
  end
  //日期以及日期设置显示
  else if((Date_EN || DateSet_EN) == 1'b1)
  begin
    disp_select <= date_disp_select;
    case(date_disp_select)
      6'b100000: Data <= month1;
      6'b010000: Data <= month0;
      6'b001000: Data <= day1;
      6'b000100: Data <= day0;
      default:   Data <= 4'b0;
    endcase
  end
  //显示数据译码
  case(Data)
    4'b0000: disp_data <= 7'b1111110;
    4'b0001: disp_data <= 7'b0110000;
    4'b0010: disp_data <= 7'b1101101;
    4'b0011: disp_data <= 7'b1111001;
    4'b0100: disp_data <= 7'b0110011;
    4'b0101: disp_data <= 7'b1011011;
    4'b0110: disp_data <= 7'b1011111;
    4'b0111: disp_data <= 7'b1110000;
    4'b1000: disp_data <= 7'b1111111;
    4'b1001: disp_data <= 7'b1111011;
    default: disp_data <= 7'b0;
  endcase

end

endmodule