main.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                  ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                                                                                                                                   ; To                                                                                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A                                      ; None          ; 32.524 ns                                      ; time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] ; disp_data[6]                                                                                  ; Clock      ;          ; 0            ;
; Clock Setup: 'Clock'         ; N/A                                      ; None          ; 45.62 MHz ( period = 21.921 ns )               ; date_main:inst4|autodate:b2v_inst|EO1                                                                                                  ; date_main:inst4|datecontrol:b2v_inst1|day0[3]                                                 ; Clock      ; Clock    ; 0            ;
; Clock Setup: 'SW3'           ; N/A                                      ; None          ; 155.79 MHz ( period = 6.419 ns )               ; date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3]                                            ; date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[0] ; SW3        ; SW3      ; 0            ;
; Clock Setup: 'SW2'           ; N/A                                      ; None          ; 286.37 MHz ( period = 3.492 ns )               ; alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1]                                                       ; alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[0]              ; SW2        ; SW2      ; 0            ;
; Clock Setup: 'SW1'           ; N/A                                      ; None          ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0]                                                                                ; time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1]                                       ; SW1        ; SW1      ; 0            ;
; Clock Hold: 'SW3'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; maincontrol:inst3|DateSet_EN                                                                                                           ; date_main:inst4|autodate:b2v_inst|EO1                                                         ; SW3        ; SW3      ; 53           ;
; Clock Hold: 'Clock'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; time_disp_select:inst6|auto_disp_drive[1]                                                                                              ; time_disp_select:inst6|time_disp_select[3]                                                    ; Clock      ; Clock    ; 26           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                                                                                                        ;                                                                                               ;            ;          ; 79           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


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