timeset.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register disp_drive\[0\]~reg0 register disp_drive\[2\]~reg0 172.41 MHz 5.8 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 172.41 MHz between source register \"disp_drive\[0\]~reg0\" and destination register \"disp_drive\[2\]~reg0\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register register " "Info: + Longest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns disp_drive\[0\]~reg0 1 REG LC1 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns disp_drive\[2\]~reg0 2 REG LC3 27 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 27; REG Node = 'disp_drive\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.800 ns" { disp_drive[0]~reg0 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 68.42 % " "Info: Total cell delay = 2.600 ns ( 68.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 31.58 % " "Info: Total interconnect delay = 1.200 ns ( 31.58 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.800 ns" { disp_drive[0]~reg0 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { disp_drive[0]~reg0 disp_drive[2]~reg0 } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW1 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW1 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_drive\[2\]~reg0 2 REG LC3 27 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC3; Fanout = 27; REG Node = 'disp_drive\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW1 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW1 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW1 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_drive\[0\]~reg0 2 REG LC1 27 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.800 ns" { disp_drive[0]~reg0 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { disp_drive[0]~reg0 disp_drive[2]~reg0 } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register lpm_counter:minute_set0_rtl_3\|dffs\[0\] register lpm_counter:minute_set0_rtl_3\|dffs\[1\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 175.44 MHz between source register \"lpm_counter:minute_set0_rtl_3\|dffs\[0\]\" and destination register \"lpm_counter:minute_set0_rtl_3\|dffs\[1\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:minute_set0_rtl_3\|dffs\[0\] 1 REG LC21 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { lpm_counter:minute_set0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns lpm_counter:minute_set0_rtl_3\|dffs\[1\] 2 REG LC30 7 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC30; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.700 ns" { lpm_counter:minute_set0_rtl_3|dffs[0] lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.700 ns" { lpm_counter:minute_set0_rtl_3|dffs[0] lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { lpm_counter:minute_set0_rtl_3|dffs[0] lpm_counter:minute_set0_rtl_3|dffs[1] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW2 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:minute_set0_rtl_3\|dffs\[1\] 2 REG LC30 7 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC30; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW2 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:minute_set0_rtl_3\|dffs\[0\] 2 REG LC21 8 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC21; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.700 ns" { lpm_counter:minute_set0_rtl_3|dffs[0] lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { lpm_counter:minute_set0_rtl_3|dffs[0] lpm_counter:minute_set0_rtl_3|dffs[1] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}