timeset.map.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 17:45:11 2006 " "Info: Processing started: Sat Jul 15 17:45:11 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off timeset -c timeset --generate_symbol=E:\\戴仙金\\资料\\Verilog书\\源代码\\wristwatch\\timeset\\timeset.v " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off timeset -c timeset --generate_symbol=E:\\戴仙金\\资料\\Verilog书\\源代码\\wristwatch\\timeset\\timeset.v" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartu