timeset.fit.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Sat Jul 15 17:44:29 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : timeset
Top-level Entity Name : timeset
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 27 / 64 ( 42 % )
Total pins : 58 / 68 ( 85 % )
Device : EPM7064STC100-5
Timing Models : Final