timeset.map.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

;    |lpm_counter:minute_set0_rtl_3| ; 4          ; 0    ; |timeset|lpm_counter:minute_set0_rtl_3 ;
;    |lpm_counter:minute_set1_rtl_2| ; 3          ; 0    ; |timeset|lpm_counter:minute_set1_rtl_2 ;
;    |lpm_counter:second_set0_rtl_5| ; 4          ; 0    ; |timeset|lpm_counter:second_set0_rtl_5 ;
;    |lpm_counter:second_set1_rtl_4| ; 3          ; 0    ; |timeset|lpm_counter:second_set1_rtl_4 ;
+------------------------------------+------------+------+----------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; timeset.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v        ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 27                   ;
; Total registers      ; 23                   ;
; I/O pins             ; 54                   ;
; Maximum fan-out node ; disp_drive[0]~reg0   ;
; Maximum fan-out      ; 24                   ;
; Total fan-out        ; 189                  ;
; Average fan-out      ; 2.33                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 17:44:21 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off timeset -c timeset
Info: Found 1 design units, including 1 entities, in source file timeset.v
    Info: Found entity 1: timeset
Warning: Verilog HDL unsupported feature warning at timeset.v(36): Initial Construct is not supported and will be ignored
Info: Inferred 6 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour_set1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour_set0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "minute_set1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "minute_set0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "second_set1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "second_set0[0]~8"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: Reduced register "lpm_counter:hour_set1_rtl_0|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "lpm_counter:hour_set1_rtl_0|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "lpm_counter:minute_set1_rtl_2|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "lpm_counter:second_set1_rtl_4|dffs[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "hour_set1[3]" stuck at GND
    Warning: Pin "hour_set1[2]" stuck at GND
    Warning: Pin "minute_set1[3]" stuck at GND
    Warning: Pin "second_set1[3]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "SW2" to global clock signal
    Info: Promoted clock signal driven by pin "SW1" to global clock signal
Warning: Design contains 24 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "hour1[3]"
    Warning: No output dependent on input pin "hour1[2]"
    Warning: No output dependent on input pin "hour1[1]"
    Warning: No output dependent on input pin "hour1[0]"
    Warning: No output dependent on input pin "hour0[3]"
    Warning: No output dependent on input pin "hour0[2]"
    Warning: No output dependent on input pin "hour0[1]"
    Warning: No output dependent on input pin "hour0[0]"
    Warning: No output dependent on input pin "minute1[3]"
    Warning: No output dependent on input pin "minute1[2]"
    Warning: No output dependent on input pin "minute1[1]"
    Warning: No output dependent on input pin "minute1[0]"
    Warning: No output dependent on input pin "minute0[3]"
    Warning: No output dependent on input pin "minute0[2]"
    Warning: No output dependent on input pin "minute0[1]"
    Warning: No output dependent on input pin "minute0[0]"
    Warning: No output dependent on input pin "second1[3]"
    Warning: No output dependent on input pin "second1[2]"
    Warning: No output dependent on input pin "second1[1]"
    Warning: No output dependent on input pin "second1[0]"
    Warning: No output dependent on input pin "second0[3]"
    Warning: No output dependent on input pin "second0[2]"
    Warning: No output dependent on input pin "second0[1]"
    Warning: No output dependent on input pin "second0[0]"
Info: Implemented 81 device resources after synthesis - the final resource count might be different
    Info: Implemented 27 input pins
    Info: Implemented 27 output pins
    Info: Implemented 27 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Sat Jul 15 17:44:25 2006
    Info: Elapsed time: 00:00:05