timeset.tan.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.900 ns
From           : TimeSet_EN
To             : disp_drive[2]~reg0
From Clock     : 
To Clock       : SW1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 3.200 ns
From           : disp_drive[0]~reg0
To             : disp_drive[0]
From Clock     : SW1
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.400 ns
From           : TimeSet_EN
To             : disp_drive[2]~reg0
From Clock     : 
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW1'
Slack          : N/A
Required Time  : None
Actual Time    : 172.41 MHz ( period = 5.800 ns )
From           : disp_drive[2]~reg0
To             : disp_drive[0]~reg0
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW2'
Slack          : N/A
Required Time  : None
Actual Time    : 175.44 MHz ( period = 5.700 ns )
From           : lpm_counter:hour_set1_rtl_0|dffs[1]
To             : lpm_counter:hour_set1_rtl_0|dffs[0]
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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