alarmclock.hier_info

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

|alarmclock
clk_200hz => alarmclock_disp_select[4]~reg0.CLK
clk_200hz => alarmclock_disp_select[3]~reg0.CLK
clk_200hz => alarmclock_disp_select[2]~reg0.CLK
clk_200hz => alarmclock_disp_select[1]~reg0.CLK
clk_200hz => alarmclock_disp_select[0]~reg0.CLK
clk_200hz => alarmclock_disp_select[5]~reg0.CLK
EN => disp_drive~3.OUTPUTSELECT
EN => disp_drive~4.OUTPUTSELECT
EN => disp_drive~5.OUTPUTSELECT
SW1 => disp_drive[1].CLK
SW1 => disp_drive[0].CLK
SW1 => disp_drive[2].CLK
SW2 => hour_set1[2].CLK
SW2 => hour_set1[1].CLK
SW2 => hour_set1[0].CLK
SW2 => hour_set0[3].CLK
SW2 => hour_set0[2].CLK
SW2 => hour_set0[1].CLK
SW2 => hour_set0[0].CLK
SW2 => minute_set1[3].CLK
SW2 => minute_set1[2].CLK
SW2 => minute_set1[1].CLK
SW2 => minute_set1[0].CLK
SW2 => minute_set0[3].CLK
SW2 => minute_set0[2].CLK
SW2 => minute_set0[1].CLK
SW2 => minute_set0[0].CLK
SW2 => second_set1[3].CLK
SW2 => second_set1[2].CLK
SW2 => second_set1[1].CLK
SW2 => second_set1[0].CLK
SW2 => second_set0[3].CLK
SW2 => second_set0[2].CLK
SW2 => second_set0[1].CLK
SW2 => second_set0[0].CLK
SW2 => hour_set1[3].CLK
hour1[0] => always0~0.IN0
hour1[1] => always0~1.IN0
hour1[2] => always0~2.IN0
hour1[3] => always0~3.IN0
hour0[0] => always0~4.IN0
hour0[1] => always0~5.IN0
hour0[2] => always0~6.IN0
hour0[3] => always0~7.IN0
minute1[0] => always0~9.IN0
minute1[1] => always0~10.IN0
minute1[2] => always0~11.IN0
minute1[3] => always0~12.IN0
minute0[0] => always0~14.IN0
minute0[1] => always0~15.IN0
minute0[2] => always0~16.IN0
minute0[3] => always0~17.IN0
second1[0] => always0~19.IN0
second1[1] => always0~20.IN0
second1[2] => always0~21.IN0
second1[3] => always0~22.IN0
second0[0] => always0~24.IN0
second0[1] => always0~25.IN0
second0[2] => always0~26.IN0
second0[3] => always0~27.IN0
alarm <= alarm~0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[0] <= alarmclock_disp_select[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[1] <= alarmclock_disp_select[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[2] <= alarmclock_disp_select[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[3] <= alarmclock_disp_select[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[4] <= alarmclock_disp_select[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[5] <= alarmclock_disp_select[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE