alarmclock.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_200hz " "Info: Assuming node \"clk_200hz\" is an undefined clock" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_200hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register disp_drive\[0\] register disp_drive\[2\] 169.49 MHz 5.9 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 169.49 MHz between source register \"disp_drive\[0\]\" and destination register \"disp_drive\[2\]\" (period= 5.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest register register " "Info: + Longest register to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns disp_drive\[0\] 1 REG LC18 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(2.600 ns) 3.900 ns disp_drive\[2\] 2 REG LC20 29 " "Info: 2: + IC(1.300 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC20; Fanout = 29; REG Node = 'disp_drive\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { disp_drive[0] disp_drive[2] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 66.67 % " "Info: Total cell delay = 2.600 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns 33.33 % " "Info: Total interconnect delay = 1.300 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { disp_drive[0] disp_drive[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { disp_drive[0] disp_drive[2] } { 0.000ns 1.300ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 4.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW1 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.700 ns) 4.000 ns disp_drive\[2\] 2 REG LC20 29 " "Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC20; Fanout = 29; REG Node = 'disp_drive\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { SW1 disp_drive[2] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 72.50 % " "Info: Total cell delay = 2.900 ns ( 72.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 27.50 % " "Info: Total interconnect delay = 1.100 ns ( 27.50 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[2] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 4.000 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW1 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.700 ns) 4.000 ns disp_drive\[0\] 2 REG LC18 31 " "Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 72.50 % " "Info: Total cell delay = 2.900 ns ( 72.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 27.50 % " "Info: Total interconnect delay = 1.100 ns ( 27.50 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[2] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { disp_drive[0] disp_drive[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { disp_drive[0] disp_drive[2] } { 0.000ns 1.300ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[2] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_200hz " "Info: No valid register-to-register data paths exist for clock \"clk_200hz\"" {  } {  } 0}