alarmclock.tan.rpt

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· RPT 代码 · 共 387 行 · 第 1/3 页

; N/A   ; None              ; 9.600 ns        ; hour1[0]   ; alarm ;
; N/A   ; None              ; 9.600 ns        ; hour1[1]   ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second0[0] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second0[1] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second0[2] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second0[3] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second1[0] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second1[1] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; second1[2] ; alarm ;
; N/A   ; None              ; 8.100 ns        ; minute0[0] ; alarm ;
; N/A   ; None              ; 5.000 ns        ; second1[3] ; alarm ;
; N/A   ; None              ; 5.000 ns        ; minute1[3] ; alarm ;
; N/A   ; None              ; 5.000 ns        ; hour1[2]   ; alarm ;
; N/A   ; None              ; 5.000 ns        ; hour1[3]   ; alarm ;
+-------+-------------------+-----------------+------------+-------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; 1.800 ns  ; EN   ; disp_drive[0] ; SW1      ;
; N/A           ; None        ; 1.800 ns  ; EN   ; disp_drive[1] ; SW1      ;
; N/A           ; None        ; 1.800 ns  ; EN   ; disp_drive[2] ; SW1      ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 20:29:48 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off alarmclock -c alarmclock
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SW1" is an undefined clock
    Info: Assuming node "clk_200hz" is an undefined clock
    Info: Assuming node "SW2" is an undefined clock
Info: Clock "SW1" has Internal fmax of 169.49 MHz between source register "disp_drive[0]" and destination register "disp_drive[2]" (period= 5.9 ns)
    Info: + Longest register to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
        Info: 2: + IC(1.300 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC20; Fanout = 29; REG Node = 'disp_drive[2]'
        Info: Total cell delay = 2.600 ns ( 66.67 % )
        Info: Total interconnect delay = 1.300 ns ( 33.33 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW1" to destination register is 4.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'
            Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC20; Fanout = 29; REG Node = 'disp_drive[2]'
            Info: Total cell delay = 2.900 ns ( 72.50 % )
            Info: Total interconnect delay = 1.100 ns ( 27.50 % )
        Info: - Longest clock path from clock "SW1" to source register is 4.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'
            Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
            Info: Total cell delay = 2.900 ns ( 72.50 % )
            Info: Total interconnect delay = 1.100 ns ( 27.50 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: No valid register-to-register data paths exist for clock "clk_200hz"
Info: Clock "SW2" has Internal fmax of 172.41 MHz between source register "lpm_counter:second_set1_rtl_1|dffs[1]" and destination register "lpm_counter:second_set1_rtl_1|dffs[0]" (period= 5.8 ns)
    Info: + Longest register to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 7; REG Node = 'lpm_counter:second_set1_rtl_1|dffs[1]'
        Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC13; Fanout = 8; REG Node = 'lpm_counter:second_set1_rtl_1|dffs[0]'
        Info: Total cell delay = 2.600 ns ( 68.42 % )
        Info: Total interconnect delay = 1.200 ns ( 31.58 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW2" to destination register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC13; Fanout = 8; REG Node = 'lpm_counter:second_set1_rtl_1|dffs[0]'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW2" to source register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC11; Fanout = 7; REG Node = 'lpm_counter:second_set1_rtl_1|dffs[1]'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "disp_drive[0]" (data pin = "EN", clock pin = "SW1") is 0.700 ns
    Info: + Longest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_46; Fanout = 5; PIN Node = 'EN'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "SW1" to destination register is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'
        Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
        Info: Total cell delay = 2.900 ns ( 72.50 % )
        Info: Total interconnect delay = 1.100 ns ( 27.50 % )
Info: tco from clock "SW2" to destination pin "alarm" through register "lpm_counter:minute_set0_rtl_2|dffs[1]" is 12.400 ns
    Info: + Longest clock path from clock "SW2" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC37; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_2|dffs[1]'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Longest register to pin delay is 9.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_2|dffs[1]'
        Info: 2: + IC(1.100 ns) + CELL(3.500 ns) = 4.600 ns; Loc. = LC38; Fanout = 1; COMB Node = 'always0~68'
        Info: 3: + IC(1.100 ns) + CELL(3.500 ns) = 9.200 ns; Loc. = LC49; Fanout = 1; COMB Node = 'always0~117'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.400 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'alarm'
        Info: Total cell delay = 7.200 ns ( 76.60 % )
        Info: Total interconnect delay = 2.200 ns ( 23.40 % )
Info: Longest tpd from source pin "minute0[1]" to destination pin "alarm" is 9.600 ns
    Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 1; PIN Node = 'minute0[1]'
    Info: 2: + IC(1.100 ns) + CELL(3.500 ns) = 4.800 ns; Loc. = LC38; Fanout = 1; COMB Node = 'always0~68'
    Info: 3: + IC(1.100 ns) + CELL(3.500 ns) = 9.400 ns; Loc. = LC49; Fanout = 1; COMB Node = 'always0~117'
    Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.600 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'alarm'
    Info: Total cell delay = 7.400 ns ( 77.08 % )
    Info: Total interconnect delay = 2.200 ns ( 22.92 % )
Info: th for register "disp_drive[0]" (data pin = "EN", clock pin = "SW1") is 1.800 ns
    Info: + Longest clock path from clock "SW1" to destination register is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'
        Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
        Info: Total cell delay = 2.900 ns ( 72.50 % )
        Info: Total interconnect delay = 1.100 ns ( 27.50 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_46; Fanout = 5; PIN Node = 'EN'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive[0]'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 15 20:29:49 2006
    Info: Elapsed time: 00:00:02