second_counter.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk EO EO~reg0 2.800 ns register " "Info: tco from clock \"clk\" to destination pin \"EO\" through register \"EO~reg0\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { clk } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns EO~reg0 2 REG LC7 4 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.100 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns EO~reg0 1 REG LC7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EO 2 PIN PIN_11 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.200 ns" { EO~reg0 EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.200 ns" { EO~reg0 EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { EO~reg0 EO } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.200 ns" { EO~reg0 EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { EO~reg0 EO } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:second_data0_rtl_1\|dffs\[0\] EN clk -0.800 ns register " "Info: th for register \"lpm_counter:second_data0_rtl_1\|dffs\[0\]\" (data pin = \"EN\", clock pin = \"clk\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { clk } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:second_data0_rtl_1\|dffs\[0\] 2 REG LC3 16 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 16; REG Node = 'lpm_counter:second_data0_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.100 ns" { clk lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:second_data0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN 1 PIN PIN_44 20 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 20; PIN Node = 'EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { EN } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 3.800 ns lpm_counter:second_data0_rtl_1\|dffs\[0\] 2 REG LC3 16 " "Info: 2: + IC(0.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 16; REG Node = 'lpm_counter:second_data0_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "2.600 ns" { EN lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 100.00 % " "Info: Total cell delay = 3.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "3.800 ns" { EN lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN EN~out lpm_counter:second_data0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:second_data0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "3.800 ns" { EN lpm_counter:second_data0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN EN~out lpm_counter:second_data0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 10:20:23 2006 " "Info: Processing ended: Thu Jul 13 10:20:23 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}