second_counter.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:second_data0_rtl_1\|dffs\[3\] register EO~reg0 151.52 MHz 6.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.52 MHz between source register \"lpm_counter:second_data0_rtl_1\|dffs\[3\]\" and destination register \"EO~reg0\" (period= 6.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:second_data0_rtl_1\|dffs\[3\] 1 REG LC13 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 24; REG Node = 'lpm_counter:second_data0_rtl_1\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { lpm_counter:second_data0_rtl_1|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns LessThan~76 2 COMB LC6 1 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 1; COMB Node = 'LessThan~76'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "3.600 ns" { lpm_counter:second_data0_rtl_1|dffs[3] LessThan~76 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.500 ns EO~reg0 3 REG LC7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.500 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.900 ns" { LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "4.500 ns" { lpm_counter:second_data0_rtl_1|dffs[3] LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { lpm_counter:second_data0_rtl_1|dffs[3] LessThan~76 EO~reg0 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 2.600ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { clk } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns EO~reg0 2 REG LC7 4 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.100 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { clk } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:second_data0_rtl_1\|dffs\[3\] 2 REG LC13 24 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC13; Fanout = 24; REG Node = 'lpm_counter:second_data0_rtl_1\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.100 ns" { clk lpm_counter:second_data0_rtl_1|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk lpm_counter:second_data0_rtl_1|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:second_data0_rtl_1|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk lpm_counter:second_data0_rtl_1|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:second_data0_rtl_1|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "4.500 ns" { lpm_counter:second_data0_rtl_1|dffs[3] LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { lpm_counter:second_data0_rtl_1|dffs[3] LessThan~76 EO~reg0 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 2.600ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk lpm_counter:second_data0_rtl_1|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:second_data0_rtl_1|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "EO~reg0 EN clk 4.200 ns register " "Info: tsu for register \"EO~reg0\" (data pin = \"EN\", clock pin = \"clk\") is 4.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest pin register " "Info: + Longest pin to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN 1 PIN PIN_44 20 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 20; PIN Node = 'EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { EN } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 3.800 ns LessThan~76 2 COMB LC6 1 " "Info: 2: + IC(0.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 1; COMB Node = 'LessThan~76'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "2.600 ns" { EN LessThan~76 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.700 ns EO~reg0 3 REG LC7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.900 ns" { LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 100.00 % " "Info: Total cell delay = 4.700 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "4.700 ns" { EN LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { EN EN~out LessThan~76 EO~reg0 } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 2.600ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "" { clk } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns EO~reg0 2 REG LC7 4 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "0.100 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/second_counter.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "4.700 ns" { EN LessThan~76 EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { EN EN~out LessThan~76 EO~reg0 } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 2.600ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter_cmp.qrpt" Compiler "second_counter" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/db/second_counter.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/second_counter/" "" "1.300 ns" { clk EO~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out EO~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}