second_counter.hier_info

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

|second_counter
EN => second_data0~4.OUTPUTSELECT
EN => second_data0~5.OUTPUTSELECT
EN => second_data0~6.OUTPUTSELECT
EN => second_data0~7.OUTPUTSELECT
EN => EO~1.OUTPUTSELECT
EN => second_data1~8.OUTPUTSELECT
EN => second_data1~9.OUTPUTSELECT
EN => second_data1~10.OUTPUTSELECT
EN => second_data1~11.OUTPUTSELECT
clk => second_data0[2]~reg0.CLK
clk => second_data0[1]~reg0.CLK
clk => second_data0[0]~reg0.CLK
clk => EO~reg0.CLK
clk => second_data1[3]~reg0.CLK
clk => second_data1[2]~reg0.CLK
clk => second_data1[1]~reg0.CLK
clk => second_data1[0]~reg0.CLK
clk => second_data0[3]~reg0.CLK
second_data1[0] <= second_data1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[1] <= second_data1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[2] <= second_data1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[3] <= second_data1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[0] <= second_data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[1] <= second_data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[2] <= second_data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[3] <= second_data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
EO <= EO~reg0.DB_MAX_OUTPUT_PORT_TYPE