second_counter.map.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Thu Jul 13 10:20:15 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : second_counter
Top-level Entity Name : second_counter
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 12
Total pins : 11