second_counter.fit.eqn

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--B1_dffs[0] is lpm_counter:second_data0_rtl_1|dffs[0] at LC3
B1_dffs[0]_p1_out = !B1_dffs[0] & !B1_dffs[3];
B1_dffs[0]_p2_out = !B1_dffs[0] & !B1_dffs[2] & !B1_dffs[1];
B1_dffs[0]_or_out = B1_dffs[0]_p1_out # B1_dffs[0]_p2_out;
B1_dffs[0]_reg_input = B1_dffs[0]_or_out;
B1_dffs[0] = DFFE(B1_dffs[0]_reg_input, GLOBAL(clk), , , EN);


--B1_dffs[1] is lpm_counter:second_data0_rtl_1|dffs[1] at LC8
B1_dffs[1]_p1_out = !B1_dffs[3] & B1_dffs[1] & !B1_dffs[0];
B1_dffs[1]_p2_out = !B1_dffs[3] & !B1_dffs[1] & B1_dffs[0];
B1_dffs[1]_or_out = B1_dffs[1]_p1_out # B1_dffs[1]_p2_out;
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = DFFE(B1_dffs[1]_reg_input, GLOBAL(clk), , , EN);


--B1_dffs[2] is lpm_counter:second_data0_rtl_1|dffs[2] at LC11
B1_dffs[2]_p1_out = !B1_dffs[3] & B1_dffs[1] & B1_dffs[0];
B1_dffs[2]_p2_out = B1_dffs[3] & B1_dffs[2];
B1_dffs[2]_or_out = B1_dffs[2]_p1_out # B1_dffs[2]_p2_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = TFFE(B1_dffs[2]_reg_input, GLOBAL(clk), , , EN);


--B1_dffs[3] is lpm_counter:second_data0_rtl_1|dffs[3] at LC13
B1_dffs[3]_p1_out = B1_dffs[2] & B1_dffs[1] & B1_dffs[0] & !B1_dffs[3];
B1_dffs[3]_p2_out = !B1_dffs[2] & !B1_dffs[1] & !B1_dffs[0] & B1_dffs[3];
B1_dffs[3]_or_out = B1_dffs[3]_p1_out # B1_dffs[3]_p2_out;
B1_dffs[3]_reg_input = B1_dffs[3]_or_out;
B1_dffs[3] = DFFE(B1_dffs[3]_reg_input, GLOBAL(clk), , , EN);


--B2_dffs[0] is lpm_counter:second_data1_rtl_0|dffs[0] at LC14
B2_dffs[0]_p1_out = B2_dffs[2] & B2_dffs[1] & !B2_dffs[0];
B2_dffs[0]_p2_out = !B1_dffs[2] & !B1_dffs[1] & !B1_dffs[0];
B2_dffs[0]_or_out = B2_dffs[0]_p1_out # B2_dffs[0]_p2_out # !EN # !B1_dffs[3];
B2_dffs[0]_reg_input = !B2_dffs[0]_or_out;
B2_dffs[0] = TFFE(B2_dffs[0]_reg_input, GLOBAL(clk), , , );


--B2_dffs[1] is lpm_counter:second_data1_rtl_0|dffs[1] at LC2
B2_dffs[1]_p0_out = !B2_dffs[2] & !B2_dffs[0] & B2_dffs[1];
B2_dffs[1]_p1_out = !B2_dffs[2] & B2_dffs[0] & !B2_dffs[1] & EN & B1_dffs[3] & B1_dffs[2];
B2_dffs[1]_p2_out = B2_dffs[1] & !EN;
B2_dffs[1]_p3_out = !B2_dffs[2] & B2_dffs[0] & !B2_dffs[1] & EN & B1_dffs[3] & B1_dffs[0];
B2_dffs[1]_p4_out = !B2_dffs[2] & B2_dffs[0] & !B2_dffs[1] & EN & B1_dffs[3] & B1_dffs[1];
B2_dffs[1]_or_out = B2L4 # B2_dffs[1]_p0_out # B2_dffs[1]_p1_out # B2_dffs[1]_p2_out # B2_dffs[1]_p3_out # B2_dffs[1]_p4_out;
B2_dffs[1]_reg_input = B2_dffs[1]_or_out;
B2_dffs[1] = DFFE(B2_dffs[1]_reg_input, GLOBAL(clk), , , );


--B2_dffs[2] is lpm_counter:second_data1_rtl_0|dffs[2] at LC5
B2_dffs[2]_p0_out = !B2_dffs[1] & !B2_dffs[0] & B2_dffs[2];
B2_dffs[2]_p1_out = B2_dffs[1] & B2_dffs[0] & EN & B1_dffs[3] & !B2_dffs[2] & B1_dffs[2];
B2_dffs[2]_p2_out = !EN & B2_dffs[2];
B2_dffs[2]_p3_out = B2_dffs[1] & B2_dffs[0] & EN & B1_dffs[3] & !B2_dffs[2] & B1_dffs[0];
B2_dffs[2]_p4_out = B2_dffs[1] & B2_dffs[0] & EN & B1_dffs[3] & !B2_dffs[2] & B1_dffs[1];
B2_dffs[2]_or_out = B2L6 # B2_dffs[2]_p0_out # B2_dffs[2]_p1_out # B2_dffs[2]_p2_out # B2_dffs[2]_p3_out # B2_dffs[2]_p4_out;
B2_dffs[2]_reg_input = B2_dffs[2]_or_out;
B2_dffs[2] = DFFE(B2_dffs[2]_reg_input, GLOBAL(clk), , , );


--A1L3Q is EO~reg0 at LC7
A1L3Q_p0_out = !B1_dffs[0] & A1L3Q & !B1_dffs[2] & !B1_dffs[1];
A1L3Q_p1_out = B2_dffs[1] & B2_dffs[2] & EN & B1_dffs[3] & B1_dffs[0];
A1L3Q_p2_out = B2_dffs[2] & EN & B1_dffs[3] & B1_dffs[0] & B2_dffs[0];
A1L3Q_p3_out = !EN & A1L3Q;
A1L3Q_p4_out = !B1_dffs[3] & A1L3Q;
A1L3Q_or_out = A1L4 # A1L3Q_p0_out # A1L3Q_p1_out # A1L3Q_p2_out # A1L3Q_p3_out # A1L3Q_p4_out;
A1L3Q_reg_input = A1L3Q_or_out;
A1L3Q = DFFE(A1L3Q_reg_input, GLOBAL(clk), , , );


--B2L4 is lpm_counter:second_data1_rtl_0|dffs[1]~145 at LC1
B2L4_p1_out = B2_dffs[1] & !B1_dffs[2] & !B1_dffs[1] & !B1_dffs[0];
B2L4_p2_out = B2_dffs[1] & !B1_dffs[3];
B2L4 = B2L4_p1_out # B2L4_p2_out;


--B2L6 is lpm_counter:second_data1_rtl_0|dffs[2]~148 at LC4
B2L6_p1_out = B2_dffs[2] & !B1_dffs[2] & !B1_dffs[1] & !B1_dffs[0];
B2L6_p2_out = B2_dffs[2] & !B1_dffs[3];
B2L6 = B2L6_p1_out # B2L6_p2_out;


--A1L4 is LessThan~76 at LC6
A1L4_p1_out = B2_dffs[1] & B2_dffs[2] & EN & B1_dffs[3] & B1_dffs[2];
A1L4_p2_out = B2_dffs[2] & EN & B1_dffs[3] & B1_dffs[2] & B2_dffs[0];
A1L4_p3_out = B2_dffs[1] & B2_dffs[2] & EN & B1_dffs[3] & B1_dffs[1];
A1L4_p4_out = B2_dffs[2] & EN & B1_dffs[3] & B2_dffs[0] & B1_dffs[1];
A1L4 = A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;


--~GND~0 is ~GND~0 at LC10
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--EN is EN at PIN_44
--operation mode is input

EN = INPUT();


--clk is clk at PIN_43
--operation mode is input

clk = INPUT();


--second_data1[3] is second_data1[3] at PIN_14
--operation mode is output

second_data1[3] = OUTPUT(~GND~0);


--second_data0[0] is second_data0[0] at PIN_6
--operation mode is output

second_data0[0] = OUTPUT(B1_dffs[0]);


--second_data0[1] is second_data0[1] at PIN_12
--operation mode is output

second_data0[1] = OUTPUT(B1_dffs[1]);


--second_data0[2] is second_data0[2] at PIN_16
--operation mode is output

second_data0[2] = OUTPUT(B1_dffs[2]);


--second_data0[3] is second_data0[3] at PIN_18
--operation mode is output

second_data0[3] = OUTPUT(B1_dffs[3]);


--second_data1[0] is second_data1[0] at PIN_19
--operation mode is output

second_data1[0] = OUTPUT(B2_dffs[0]);


--second_data1[1] is second_data1[1] at PIN_5
--operation mode is output

second_data1[1] = OUTPUT(B2_dffs[1]);


--second_data1[2] is second_data1[2] at PIN_8
--operation mode is output

second_data1[2] = OUTPUT(B2_dffs[2]);


--EO is EO at PIN_11
--operation mode is output

EO = OUTPUT(A1L3Q);