second_counter.tan.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.200 ns
From           : EN
To             : EO~reg0
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : lpm_counter:second_data0_rtl_1|dffs[0]
To             : second_data0[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.800 ns
From           : EN
To             : EO~reg0
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 151.52 MHz ( period = 6.600 ns )
From           : lpm_counter:second_data1_rtl_0|dffs[2]
To             : lpm_counter:second_data1_rtl_0|dffs[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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