second_counter.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[0] ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[3] ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[2] ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[1] ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[0] ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[3] ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[2] ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[1] ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[0] ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[3] ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[2] ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:second_data0_rtl_1|dffs[1] ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+----------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------+
; tsu                                                                                          ;
+-------+--------------+------------+------+----------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                                     ; To Clock ;
+-------+--------------+------------+------+----------------------------------------+----------+
; N/A   ; None         ; 4.200 ns   ; EN   ; EO~reg0                                ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data0_rtl_1|dffs[1] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data1_rtl_0|dffs[0] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data1_rtl_0|dffs[2] ; clk      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:second_data1_rtl_0|dffs[1] ; clk      ;
+-------+--------------+------------+------+----------------------------------------+----------+


+-----------------------------------------------------------------------------------------------------------+
; tco                                                                                                       ;
+-------+--------------+------------+----------------------------------------+-----------------+------------+
; Slack ; Required tco ; Actual tco ; From                                   ; To              ; From Clock ;
+-------+--------------+------------+----------------------------------------+-----------------+------------+
; N/A   ; None         ; 2.800 ns   ; EO~reg0                                ; EO              ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data1_rtl_0|dffs[2] ; second_data1[2] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data1_rtl_0|dffs[1] ; second_data1[1] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data1_rtl_0|dffs[0] ; second_data1[0] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data0_rtl_1|dffs[3] ; second_data0[3] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data0_rtl_1|dffs[2] ; second_data0[2] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data0_rtl_1|dffs[1] ; second_data0[1] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:second_data0_rtl_1|dffs[0] ; second_data0[0] ; clk        ;
+-------+--------------+------------+----------------------------------------+-----------------+------------+


+----------------------------------------------------------------------------------------------------+
; th                                                                                                 ;
+---------------+-------------+-----------+------+----------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                     ; To Clock ;
+---------------+-------------+-----------+------+----------------------------------------+----------+
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data0_rtl_1|dffs[0] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data0_rtl_1|dffs[3] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data0_rtl_1|dffs[2] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data0_rtl_1|dffs[1] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data1_rtl_0|dffs[0] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data1_rtl_0|dffs[2] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; lpm_counter:second_data1_rtl_0|dffs[1] ; clk      ;
; N/A           ; None        ; -0.800 ns ; EN   ; EO~reg0                                ; clk      ;
+---------------+-------------+-----------+------+----------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jul 13 10:20:22 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off second_counter -c second_counter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 151.52 MHz between source register "lpm_counter:second_data0_rtl_1|dffs[3]" and destination register "EO~reg0" (period= 6.6 ns)
    Info: + Longest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 24; REG Node = 'lpm_counter:second_data0_rtl_1|dffs[3]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 1; COMB Node = 'LessThan~76'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.500 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
        Info: Total cell delay = 3.500 ns ( 77.78 % )
        Info: Total interconnect delay = 1.000 ns ( 22.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC13; Fanout = 24; REG Node = 'lpm_counter:second_data0_rtl_1|dffs[3]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "EO~reg0" (data pin = "EN", clock pin = "clk") is 4.200 ns
    Info: + Longest pin to register delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 20; PIN Node = 'EN'
        Info: 2: + IC(0.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 1; COMB Node = 'LessThan~76'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
        Info: Total cell delay = 4.700 ns ( 100.00 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "EO" through register "EO~reg0" is 2.800 ns
    Info: + Longest clock path from clock "clk" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 4; REG Node = 'EO~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'EO'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "lpm_counter:second_data0_rtl_1|dffs[0]" (data pin = "EN", clock pin = "clk") is -0.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 16; REG Node = 'lpm_counter:second_data0_rtl_1|dffs[0]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 20; PIN Node = 'EN'
        Info: 2: + IC(0.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 16; REG Node = 'lpm_counter:second_data0_rtl_1|dffs[0]'
        Info: Total cell delay = 3.800 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jul 13 10:20:23 2006
    Info: Elapsed time: 00:00:01