timepiece_main.fit.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 17:07:39 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : timepiece_main
Top-level Entity Name : timepiece_main
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 38 / 64 ( 59 % )
Total pins : 31 / 36 ( 86 % )
Device : EPM7064STC44-5
Timing Models : Final