timepiece_main.tan.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.100 ns
From           : Timepiece_EN
To             : second_counter:b2v_inst2|EO
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.500 ns
From           : hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0]
To             : hour0[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.600 ns
From           : Timepiece_EN
To             : hour_counter:b2v_inst|EO
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 149.25 MHz ( period = 6.700 ns )
From           : second_counter:b2v_inst2|lpm_counter:second_data0_rtl_4|dffs[1]
To             : second_counter:b2v_inst2|lpm_counter:second_data1_rtl_5|dffs[2]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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