timepiece_main.v

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· Verilog 代码 · 共 32 行

module timepiece_main(
	CLK,
	Timepiece_EN,
	day_EN,
	hour0,hour1,
	minute0,minute1,
	second0,second1	
);

input	CLK;
input	Timepiece_EN;
output	day_EN;
output	[3:0] hour1,hour0;
output	[3:0] minute1,minute0;
output	[3:0] second1,second0;


wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;


hour_counter	b2v_inst(.clk(SYNTHESIZED_WIRE_0),
.EN(Timepiece_EN),.EO(day_EN),.hour_data0(hour0),.hour_data1(hour1));

minute_counter	b2v_inst1(.clk(SYNTHESIZED_WIRE_1),
.EN(Timepiece_EN),.EO(SYNTHESIZED_WIRE_0),.minute_data0(minute0),.minute_data1(minute1));

second_counter	b2v_inst2(.clk(CLK),
.EN(Timepiece_EN),.EO(SYNTHESIZED_WIRE_1),.second_data0(second0),.second_data1(second1));

endmodule