timepiece_main.map.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 9 行

Flow Status : Successful - Sat Jul 15 17:07:22 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : timepiece_main
Top-level Entity Name : timepiece_main
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 38
Total pins : 27