timepiece_main.tan.rpt

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· RPT 代码 · 共 399 行 · 第 1/5 页

+---------------+-------------+-----------+--------------+-----------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 17:07:46 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off timepiece_main -c timepiece_main
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "minute_counter:b2v_inst1|EO" as buffer
    Info: Detected ripple clock "second_counter:b2v_inst2|EO" as buffer
Info: Clock "CLK" has Internal fmax of 149.25 MHz between source register "hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1]" and destination register "hour_counter:b2v_inst|EO" (period= 6.7 ns)
    Info: + Longest register to register delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC53; Fanout = 23; REG Node = 'hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1]'
        Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC45; Fanout = 1; COMB Node = 'hour_counter:b2v_inst|EO~154'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst|EO'
        Info: Total cell delay = 3.500 ns ( 74.47 % )
        Info: Total interconnect delay = 1.200 ns ( 25.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 12.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
            Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1|EO'
            Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst|EO'
            Info: Total cell delay = 9.600 ns ( 79.34 % )
            Info: Total interconnect delay = 2.500 ns ( 20.66 % )
        Info: - Longest clock path from clock "CLK" to source register is 12.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
            Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1|EO'
            Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC53; Fanout = 23; REG Node = 'hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1]'
            Info: Total cell delay = 9.600 ns ( 79.34 % )
            Info: Total interconnect delay = 2.500 ns ( 20.66 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "second_counter:b2v_inst2|EO" (data pin = "Timepiece_EN", clock pin = "CLK") is 4.100 ns
    Info: + Longest pin to register delay is 5.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 69; PIN Node = 'Timepiece_EN'
        Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC42; Fanout = 1; COMB Node = 'second_counter:b2v_inst2|LessThan~76'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.100 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
        Info: Total cell delay = 3.700 ns ( 72.55 % )
        Info: Total interconnect delay = 1.400 ns ( 27.45 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "day_EN" through register "hour_counter:b2v_inst|EO" is 13.500 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
        Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1|EO'
        Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst|EO'
        Info: Total cell delay = 9.600 ns ( 79.34 % )
        Info: Total interconnect delay = 2.500 ns ( 20.66 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst|EO'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'day_EN'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0]" (data pin = "Timepiece_EN", clock pin = "CLK") is 9.600 ns
    Info: + Longest clock path from clock "CLK" to destination register is 12.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2|EO'
        Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1|EO'
        Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC36; Fanout = 18; REG Node = 'hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0]'
        Info: Total cell delay = 9.600 ns ( 79.34 % )
        Info: Total interconnect delay = 2.500 ns ( 20.66 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 4.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 69; PIN Node = 'Timepiece_EN'
        Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC36; Fanout = 18; REG Node = 'hour_counter:b2v_