hour_counter.fit.rpt

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· RPT 代码 · 共 372 行 · 第 1/3 页

RPT
372 行
字号
123
+----------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                              ;
+-----------------------------------+------------+------+--------------------------------------------+
; Compilation Hierarchy Node        ; Macrocells ; Pins ; Full Hierarchy Name                        ;
+-----------------------------------+------------+------+--------------------------------------------+
; |hour_counter                     ; 11         ; 17   ; |hour_counter                              ;
;    |lpm_counter:hour_data0_rtl_1| ; 4          ; 0    ; |hour_counter|lpm_counter:hour_data0_rtl_1 ;
;    |lpm_counter:hour_data1_rtl_0| ; 4          ; 0    ; |hour_counter|lpm_counter:hour_data1_rtl_0 ;
+-----------------------------------+------------+------+--------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Control Signals                                                                             ;
+------+----------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+--------------+--------+----------------------+------------------+
; EN   ; PIN_21   ; 7       ; Clock enable ; no     ; --                   ; --               ;
; clk  ; PIN_43   ; 7       ; Clock        ; yes    ; On                   ; --               ;
+------+----------+---------+--------------+--------+----------------------+------------------+


+---------------------------------------------------------------------+
; Global & Other Fast Signals                                         ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk  ; PIN_43   ; 7       ; On                   ; --               ;
+------+----------+---------+----------------------+------------------+


+---------------------------------------------------+
; Non-Global High Fan-Out Signals                   ;
+-----------------------------------------+---------+
; Name                                    ; Fan-Out ;
+-----------------------------------------+---------+
; lpm_counter:hour_data1_rtl_0|dffs[1]    ; 9       ;
; lpm_counter:hour_data0_rtl_1|dffs[3]    ; 9       ;
; lpm_counter:hour_data0_rtl_1|dffs[2]    ; 9       ;
; lpm_counter:hour_data0_rtl_1|dffs[1]    ; 9       ;
; lpm_counter:hour_data0_rtl_1|dffs[0]    ; 9       ;
; lpm_counter:hour_data1_rtl_0|dffs[0]    ; 8       ;
; EN                                      ; 7       ;
; EO~reg0                                 ; 3       ;
; ~GND~1                                  ; 1       ;
; ~GND~0                                  ; 1       ;
; lpm_counter:hour_data1_rtl_0|dffs[1]~95 ; 1       ;
; lpm_counter:hour_data1_rtl_0|dffs[0]~93 ; 1       ;
+-----------------------------------------+---------+


+----------------------------------------------+
; Interconnect Usage Summary                   ;
+----------------------------+-----------------+
; Interconnect Resource Type ; Usage           ;
+----------------------------+-----------------+
; Output enables             ; 0 / 6 ( 0 % )   ;
; PIA buffers                ; 8 / 72 ( 11 % ) ;
+----------------------------+-----------------+


+----------------------------------------------------------------------+
; LAB Macrocells                                                       ;
+----------------------------------------+-----------------------------+
; Number of Macrocells  (Average = 5.50) ; Number of LABs  (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0                                      ; 1                           ;
; 1                                      ; 0                           ;
; 2                                      ; 0                           ;
; 3                                      ; 0                           ;
; 4                                      ; 0                           ;
; 5                                      ; 0                           ;
; 6                                      ; 0                           ;
; 7                                      ; 0                           ;
; 8                                      ; 0                           ;
; 9                                      ; 0                           ;
; 10                                     ; 0                           ;
; 11                                     ; 1                           ;
+----------------------------------------+-----------------------------+


+---------------------------------------------------------+
; Parallel Expander                                       ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0                        ; 0                            ;
; 1                        ; 2                            ;
+--------------------------+------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input                                                                                                                                                                                                                                                                                         ; Output                                                                                                                                                                                                                                                                                              ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
;  A  ; LC6        ; clk, lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[0], EN                                                   ; lpm_counter:hour_data0_rtl_1|dffs[0], hour_data0[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[0]~93 ;
;  A  ; LC2        ; clk, lpm_counter:hour_data1_rtl_0|dffs[0]~93, EN, lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[2]          ; lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], hour_data1[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data1_rtl_0|dffs[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[0]~93                                       ;
;  A  ; LC7        ; clk, lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[2], EN                                                   ; lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], hour_data0[1], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[0]~93 ;
;  A  ; LC8        ; clk, lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], EN                                                   ; lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[2], hour_data0[2], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[0]~93 ;
;  A  ; LC11       ; clk, lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0], EN                                                                                         ; lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[3], hour_data0[3], lpm_counter:hour_data1_rtl_0|dffs[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[1]~95 ;
;  A  ; LC10       ; clk, EN, lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0]                                                   ; lpm_counter:hour_data0_rtl_1|dffs[0], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[1], hour_data1[1], EO~reg0, lpm_counter:hour_data1_rtl_0|dffs[0]~93 ;
;  A  ; LC5        ; clk, lpm_counter:hour_data1_rtl_0|dffs[1]~95, EN, lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[3], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[2], EO~reg0, lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0] ; EO~reg0, EO, lpm_counter:hour_data1_rtl_0|dffs[1]~95                                                                                                                                                                                                                                                ;
;  A  ; LC1        ; lpm_counter:hour_data0_rtl_1|dffs[2], lpm_counter:hour_data1_rtl_0|dffs[1], lpm_counter:hour_data1_rtl_0|dffs[0], lpm_counter:hour_data0_rtl_1|dffs[1], lpm_counter:hour_data0_rtl_1|dffs[0]                                                                                                  ; lpm_counter:hour_data1_rtl_0|dffs[0]                                                                                                                                                                                                                                                                ;
;  A  ; LC4        ; lpm_counter:hour_data0_rtl_1|dffs[3], EO~reg0                                                                                                                                                                                                                                                 ; EO~reg0                                                                                                                                                                                                                                                                                             ;
;  A  ; LC12       ;                                                                                                                                                                                                                                                                                               ; hour_data1[3]                                                                                                                                                                                                                                                                                       ;
;  A  ; LC3        ;                                                                                                                                                                                                                                                                                               ; hour_data1[2]                                                                                                                                                                                                                                                                                       ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 16:26:36 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off hour_counter -c hour_counter
Info: Automatically selected device EPM7032SLC44-5 for design hour_counter
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Jul 15 16:26:37 2006
    Info: Elapsed time: 00:00:02
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hour_counter.fit.rpt - 源码说明

本页面展示了「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」中的 hour_counter.fit.rpt 源码文件，采用 RPT 编程语言编写，共 372 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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