📄 disp_data_mux.tan.qmsg
字号:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 22:44:32 2006 " "Info: Processing started: Sat Jul 15 22:44:32 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off disp_data_mux -c disp_data_mux " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off disp_data_mux -c disp_data_mux" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Data\[1\]~2856 " "Info: Node \"Data\[1\]~2856\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Data\[2\]~2852 " "Info: Node \"Data\[2\]~2852\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Data\[0\]~2848 " "Info: Node \"Data\[0\]~2848\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Data\[3\]~2844 " "Info: Node \"Data\[3\]~2844\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[0\]\$latch~10 " "Info: Node \"disp_select\[0\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[1\]\$latch~10 " "Info: Node \"disp_select\[1\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[2\]\$latch~10 " "Info: Node \"disp_select\[2\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[3\]\$latch~10 " "Info: Node \"disp_select\[3\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[4\]\$latch~10 " "Info: Node \"disp_select\[4\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_select\[5\]\$latch~10 " "Info: Node \"disp_select\[5\]\$latch~10\"" { } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Stopwatch_EN disp_data\[3\] 21.000 ns Longest " "Info: Longest tpd from source pin \"Stopwatch_EN\" to destination pin \"disp_data\[3\]\" is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Stopwatch_EN 1 PIN PIN_27 87 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_27; Fanout = 87; PIN Node = 'Stopwatch_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "" { Stopwatch_EN } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 23 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(3.700 ns) 5.700 ns Data~2923 2 COMB SEXP49 5 " "Info: 2: + IC(1.800 ns) + CELL(3.700 ns) = 5.700 ns; Loc. = SEXP49; Fanout = 5; COMB Node = 'Data~2923'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "5.500 ns" { Stopwatch_EN Data~2923 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 9.700 ns Data~2802 3 COMB LC52 3 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 9.700 ns; Loc. = LC52; Fanout = 3; COMB Node = 'Data~2802'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "4.000 ns" { Data~2923 Data~2802 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.400 ns) 15.100 ns Data\[2\]~2852 4 COMB LOOP LC79 22 " "Info: 4: + IC(0.000 ns) + CELL(5.400 ns) = 15.100 ns; Loc. = LC79; Fanout = 22; COMB LOOP Node = 'Data\[2\]~2852'" { { "Info" "ITDB_PART_OF_SCC" "Data\[2\]~2852 LC79 " "Info: Loc. = LC79; Node \"Data\[2\]~2852\"" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "" { Data[2]~2852 } "NODE_NAME" } "" } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "" { Data[2]~2852 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "5.400 ns" { Data~2802 Data[2]~2852 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 57 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.000 ns) 20.600 ns reduce_or~1099 5 COMB LC85 1 " "Info: 5: + IC(1.500 ns) + CELL(4.000 ns) = 20.600 ns; Loc. = LC85; Fanout = 1; COMB Node = 'reduce_or~1099'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "5.500 ns" { Data[2]~2852 reduce_or~1099 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 21.000 ns disp_data\[3\] 6 PIN PIN_54 0 " "Info: 6: + IC(0.000 ns) + CELL(0.400 ns) = 21.000 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'disp_data\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "0.400 ns" { reduce_or~1099 disp_data[3] } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/disp_data_mux.v" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.700 ns 84.29 % " "Info: Total cell delay = 17.700 ns ( 84.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 15.71 % " "Info: Total interconnect delay = 3.300 ns ( 15.71 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux_cmp.qrpt" Compiler "disp_data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/db/disp_data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/disp_data_mux/" "" "21.000 ns" { Stopwatch_EN Data~2923 Data~2802 Data[2]~2852 reduce_or~1099 disp_data[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.000 ns" { Stopwatch_EN Stopwatch_EN~out Data~2923 Data~2802 Data[2]~2852 reduce_or~1099 disp_data[3] } { 0.000ns 0.000ns 1.800ns 0.000ns 0.000ns 1.500ns 0.000ns } { 0.000ns 0.200ns 3.700ns 4.000ns 5.400ns 4.000ns 0.400ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 22:44:33 2006 " "Info: Processing ended: Sat Jul 15 22:44:33 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -