disp_data_mux.map.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 22:44:22 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : disp_data_mux
Top-level Entity Name : disp_data_mux
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 39
Total pins : 77