fdiv.fit.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 19:33:15 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : fdiv
Top-level Entity Name : fdiv
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 116 / 128 ( 90 % )
Total pins : 8 / 68 ( 11 % )
Device : EPM7128SLC84-6
Timing Models : Final