stopwatch.fit.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Wed Jul 12 19:14:01 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : stopwatch
Top-level Entity Name : stopwatch
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 1 / 32 ( 3 % )
Total pins : 8 / 36 ( 22 % )
Device : EPM7032SLC44-5
Timing Models : Final