stopwatch.fit.eqn

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--A1L3 is F_out~9 at LC1
A1L3_p1_out = EN & clk2;
A1L3_p2_out = !EN & clk1;
A1L3_or_out = A1L3_p1_out # A1L3_p2_out;
A1L3 = A1L3_or_out;


--clk1 is clk1 at PIN_24
--operation mode is input

clk1 = INPUT();


--clk2 is clk2 at PIN_21
--operation mode is input

clk2 = INPUT();


--EN is EN at PIN_25
--operation mode is input

EN = INPUT();


--F_out is F_out at PIN_4
--operation mode is output

F_out = OUTPUT(A1L3);