time_auto_and_set.fit.summary

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Sat Jul 15 18:08:39 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : time_auto_and_set
Top-level Entity Name : time_auto_and_set
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 81 / 128 ( 63 % )
Total pins : 37 / 68 ( 54 % )
Device : EPM7128SLC84-6
Timing Models : Final