time_auto_and_set.asm.qmsg

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· QMSG 代码 · 共 5 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 18:08:42 2006 " "Info: Processing started: Sat Jul 15 18:08:42 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off time_auto_and_set -c time_auto_and_set " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off time_auto_and_set -c time_auto_and_set" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 18:08:43 2006 " "Info: Processing ended: Sat Jul 15 18:08:43 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}