time_auto_and_set.tan.qmsg

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 17 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 18 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0}  } {  } 0}