time_auto_and_set.tan.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.700 ns
From           : Timepiece_EN
To             : timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.500 ns
From           : timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[1]
To             : hour_0[1]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.400 ns
From           : TimeSet_EN
To             : second_0[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 11.100 ns
From           : Timepiece_EN
To             : timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 125.00 MHz ( period = 8.000 ns )
From           : timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_8|dffs[1]
To             : timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_10|dffs[2]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'SW1'
Slack          : N/A
Required Time  : None
Actual Time    : 140.85 MHz ( period = 7.100 ns )
From           : timeset:b2v_inst3|disp_drive[1]
To             : timeset:b2v_inst3|disp_drive[0]
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW2'
Slack          : N/A
Required Time  : None
Actual Time    : 144.93 MHz ( period = 6.900 ns )
From           : timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[1]
To             : timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[0]
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------