📄 time_auto_and_set.map.rpt
字号:
; |lpm_counter:hour_data1_rtl_2| ; 4 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_2 ;
; |minute_counter:b2v_inst1| ; 11 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|minute_counter:b2v_inst1 ;
; |lpm_counter:minute_data0_rtl_4| ; 4 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data0_rtl_4 ;
; |lpm_counter:minute_data1_rtl_6| ; 5 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_6 ;
; |second_counter:b2v_inst2| ; 11 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|second_counter:b2v_inst2 ;
; |lpm_counter:second_data0_rtl_8| ; 4 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_8 ;
; |lpm_counter:second_data1_rtl_10| ; 5 ; 0 ; |time_auto_and_set|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_10 ;
; |timeset:b2v_inst3| ; 23 ; 0 ; |time_auto_and_set|timeset:b2v_inst3 ;
; |lpm_counter:hour_set0_rtl_1| ; 4 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:hour_set0_rtl_1 ;
; |lpm_counter:hour_set1_rtl_3| ; 2 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3 ;
; |lpm_counter:minute_set0_rtl_5| ; 4 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:minute_set0_rtl_5 ;
; |lpm_counter:minute_set1_rtl_7| ; 3 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7 ;
; |lpm_counter:second_set0_rtl_9| ; 4 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:second_set0_rtl_9 ;
; |lpm_counter:second_set1_rtl_11| ; 3 ; 0 ; |time_auto_and_set|timeset:b2v_inst3|lpm_counter:second_set1_rtl_11 ;
+--------------------------------------------+------------+------+------------------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.map.eqn.
+---------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------+
; time_auto_and_set.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v ;
; timepiece_main.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timepiece_main.v ;
; hour_counter.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/hour_counter.v ;
; minute_counter.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/minute_counter.v ;
; second_counter.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v ;
; time_mux.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_mux.v ;
; timeset.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v ;
; lpm_counter.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 81 ;
; Total registers ; 46 ;
; I/O pins ; 33 ;
; Parallel expanders ; 11 ;
; Maximum fan-out node ; Timepiece_EN ;
; Maximum fan-out ; 30 ;
; Total fan-out ; 497 ;
; Average fan-out ; 4.36 ;
+----------------------+----------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Sat Jul 15 18:08:26 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off time_auto_and_set -c time_auto_and_set
Info: Found 1 design units, including 1 entities, in source file time_auto_and_set.v
Info: Found entity 1: time_auto_and_set
Info: Using design file timepiece_main.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: timepiece_main
Info: Using design file hour_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: hour_counter
Info: Using design file minute_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: minute_counter
Info: Using design file second_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: second_counter
Info: Using design file time_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: time_mux
Info: Using design file timeset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: timeset
Warning: Verilog HDL unsupported feature warning at timeset.v(36): Initial Construct is not supported and will be ignored
Info: Inferred 12 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data0[0]~16"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|hour_set0[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data1[0]~24"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|hour_set1[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data0[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|minute_set0[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data1[0]~16"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|minute_set1[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data0[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|second_set0[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data1[0]~16"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "timeset:b2v_inst3|second_set1[0]~8"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Warning: Reduced register "timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_2|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_2|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_6|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_10|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "timeset:b2v_inst3|lpm_counter:second_set1_rtl_11|dffs[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
Warning: Pin "hour_1[3]" stuck at GND
Warning: Pin "hour_1[2]" stuck at GND
Warning: Pin "minute_1[3]" stuck at GND
Warning: Pin "second_1[3]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "SW2" to global clock signal
Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 114 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 28 output pins
Info: Implemented 81 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Sat Jul 15 18:08:34 2006
Info: Elapsed time: 00:00:09
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -