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TMS3205402Verilog HDL源码

IDE_A<0>                                                                   
IDE_A<1>                                                                   
IDE_A<2>                                                                   
IDE_A<3>                                                                   
IDE_D<0>                                                                   
IDE_D<10>                                                                  
IDE_D<11>                                                                  
IDE_D<12>                                                                  
IDE_D<13>                                                                  
IDE_D<14>                                                                  
IDE_D<15>                                                                  
IDE_D<1>                                                                   
IDE_D<2>                                                                   
IDE_D<3>                                                                   
IDE_D<4>                                                                   
IDE_D<5>                                                                   
IDE_D<6>                                                                   
IDE_D<7>                                                                   
IDE_D<8>                                                                   
IDE_D<9>                                                                   
IDE_RD                                                                     
IDE_WR                                                                     
INT3                         10.0                                          
PRAM_CE                                                                    
PRAM_RD    10.0                                                            
PRAM_WE    10.0                                                            
SLOE                                                                       
SLRD                                                                       
SLWR                                                                       

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From        P     P     R
 \            B     S     W
  \           <            
   \          7            
    \         >            
     \                     
      \                    
       \                   
        \                  
  To     \------------------

D<0>                   11.0
D<10>                  11.0
D<11>                  11.0
D<12>                  11.0
D<13>                  11.0
D<14>                  11.0
D<15>                  11.0
D<1>                   11.0
D<2>                   11.0
D<3>                   11.0
D<4>                   11.0
D<5>                   11.0
D<6>                   11.0
D<7>       10.0        11.0
D<8>                   11.0
D<9>                   11.0
DRAM_CE                    
DRAM_RD                10.0
DRAM_WE                10.0
FLASH_CE                   
FLASH_RD               10.0
FLASH_WE               10.0
IDE0_CS0                   
IDE0_CS1                   
IDE1_CS0                   
IDE1_CS1                   
IDE_A<0>                   
IDE_A<1>                   
IDE_A<2>                   
IDE_A<3>                   
IDE_D<0>               11.0
IDE_D<10>              11.0
IDE_D<11>              11.0
IDE_D<12>              11.0
IDE_D<13>              11.0
IDE_D<14>              11.0
IDE_D<15>              11.0
IDE_D<1>               11.0
IDE_D<2>               11.0
IDE_D<3>               11.0
IDE_D<4>               11.0
IDE_D<5>               11.0
IDE_D<6>               11.0
IDE_D<7>               11.0
IDE_D<8>               11.0
IDE_D<9>               11.0
IDE_RD                 10.0
IDE_WR                 10.0
INT3                       
PRAM_CE          10.0      
PRAM_RD                10.0
PRAM_WE                10.0
SLOE                   10.0
SLRD                   10.0
SLWR                   10.0

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From       I     R
 \           O     W
  \          S      
   \         T      
    \        R      
     \       B      
      \             
       \            
  To    \------------

D<0>      18.9  18.9
D<1>      18.9  18.9
D<2>      17.9  17.9
D<3>      17.9  17.9
DRAM_CE   17.9  17.9
EA<15>    10.2  10.2
EA<16>    10.2  10.2
EA<17>    10.2  10.2
EA<18>    10.2  10.2
FLASH_CE  17.9  17.9
LED<0>    10.2  10.2
LED<1>    10.2  10.2

--------------------------------------------------------------------------------
                   Setup to Clock at Pad (tSU or tSUF) (nsec)

\ From      I     R
 \          O     W
  \         S      
   \        T      
    \       R      
     \      B      
      \            
  To   \------------

A15       2.1   2.1
A<0>      2.1   2.1
A<1>      2.1   2.1
A<2>      2.1   2.1
A<3>      2.1   2.1
D<0>      2.1   2.1
D<1>      2.1   2.1
D<2>      2.1   2.1
D<3>      2.1   2.1
IS        2.1   2.1

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.