my.syr

TMS3205402Verilog HDL源码

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.01 / 5.47 s | Elapsed : 0.00 / 4.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 5.47 s | Elapsed : 0.00 / 4.00 s
 
--> Reading design: my.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "my.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "my"
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : my
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : my.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "my.v"
Module <my> compiled
No errors in compilation
Analysis of file <"my.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <my>.
WARNING:Xst:905 - "my.v" line 310: The signals <reg_card0_cs, CARD0_FLG, CARD0_DATA, reg_card1_cs, CARD1_FLG, CARD1_DATA, bootloard_cs> are missing in the sensitivity list of always block.
Module <my> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <my>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <my>.
    Related source file is "my.v".
WARNING:Xst:1777 - Inout <PD> is never used or assigned.
WARNING:Xst:647 - Input <FLAGA> is never used.
WARNING:Xst:647 - Input <IFCLK> is never used.
    Found 5-bit register for signal <EA>.
    Found 1-bit register for signal <LED0>.
    Found 16-bit tristate buffer for signal <IDE_D>.
    Found 16-bit tristate buffer for signal <D>.
    Found 8-bit tristate buffer for signal <PB>.
    Found 1-bit tristate buffer for signal <CARD0_DATA>.
    Found 1-bit tristate buffer for signal <CARD1_DATA>.
    Found 4-bit register for signal <CARD0>.
    Found 4-bit register for signal <CARD1>.
    Found 1-bit register for signal <CARD_NUM>.
    Found 4-bit up counter for signal <COUNT>.
    Found 16-bit tristate buffer for signal <DO>.
    Found 1-bit register for signal <ide_num>.
    Summary:
	inferred   1 Counter(s).
	inferred   3 D-type flip-flop(s).
	inferred  58 Tristate(s).
Unit <my> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 3
 4-bit register                    : 2
 5-bit register                    : 1
# Tristates                        : 21
 1-bit tristate buffer             : 18
 16-bit tristate buffer            : 2
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:637 - Naming conflict between signal Clk of unit CARD1 and signal CARD1_Clk of unit my : renaming CARD1_Clk to CARD1_Clk1.
WARNING:Xst:637 - Naming conflict between signal Clk of unit CARD0 and signal CARD0_Clk of unit my : renaming CARD0_Clk to CARD0_Clk1.

Optimizing unit <my> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : my.ngr
Top Level Output File Name         : my
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 114

Macro Statistics :
# Registers                        : 23
#      1-bit register              : 23
# Tristates                        : 21
#      1-bit tristate buffer       : 18
#      16-bit tristate buffer      : 2
#      8-bit tristate buffer       : 1
# Xors                             : 3
#      1-bit xor2                  : 3

Cell Usage :
# BELS                             : 258
#      AND2                        : 96
#      AND3                        : 12
#      AND4                        : 2
#      AND6                        : 2
#      AND8                        : 1
#      INV                         : 116
#      OR2                         : 25
#      OR3                         : 1
#      VCC                         : 1
#      XOR2                        : 2
# FlipFlops/Latches                : 20
#      FDC                         : 4
#      FDCE                        : 15
#      FDPE                        : 1
# Tri-States                       : 16
#      BUFE                        : 16
# IO Buffers                       : 104
#      IBUF                        : 23
#      IOBUFE                      : 42
#      OBUF                        : 39
=========================================================================
CPU : 13.70 / 19.28 s | Elapsed : 14.00 / 18.00 s
 
--> 

Total memory usage is 79548 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    0 (   0 filtered)