top.mod

TMS3205402Verilog HDL源码

MODEL
MODEL_VERSION "v1998.8";
DESIGN "top";

/* port names and type */
INPUT S:PIN59 = A15;
INPUT S:PIN15 = IS;
INPUT S:PIN31 = A<3>;
INPUT S:PIN33 = A<2>;
INPUT S:PIN34 = A<1>;
INPUT S:PIN35 = A<0>;
INPUT S:PIN143 = CPLD_RESET;
INPUT S:PIN14 = RW;
INPUT S:PIN12 = IOSTRB;
INPUT S:PIN95 = PA0;
INPUT S:PIN107 = PB<0>;
INPUT S:PIN97 = FLAGB;
INPUT S:PIN94 = PA1;
INPUT S:PIN106 = PB<1>;
INPUT S:PIN96 = FLAGC;
INPUT S:PIN105 = PB<2>;
INPUT S:PIN104 = PB<3>;
INPUT S:PIN103 = PB<4>;
INPUT S:PIN102 = PB<5>;
INPUT S:PIN101 = PB<6>;
INPUT S:PIN100 = PB<7>;
INPUT S:PIN58 = A14;
INPUT S:PIN28 = A<4>;
INPUT S:PIN16 = DS;
INPUT S:PIN13 = MSTRB;
INPUT S:PIN92 = PA3;
INPUT S:PIN17 = PS;
TRIOUT S:PIN53 = D<3>;
TRIOUT S:PIN57 = D<0>;
TRIOUT S:PIN56 = D<1>;
TRIOUT S:PIN54 = D<2>;
TRIOUT S:PIN132 = IDE_D<0>;
TRIOUT S:PIN118 = IDE_D<10>;
TRIOUT S:PIN120 = IDE_D<11>;
TRIOUT S:PIN124 = IDE_D<12>;
TRIOUT S:PIN126 = IDE_D<13>;
TRIOUT S:PIN129 = IDE_D<14>;
TRIOUT S:PIN130 = IDE_D<1>;
TRIOUT S:PIN128 = IDE_D<2>;
TRIOUT S:PIN125 = IDE_D<3>;
TRIOUT S:PIN121 = IDE_D<4>;
TRIOUT S:PIN119 = IDE_D<5>;
TRIOUT S:PIN117 = IDE_D<6>;
TRIOUT S:PIN115 = IDE_D<7>;
TRIOUT S:PIN113 = IDE_D<8>;
TRIOUT S:PIN116 = IDE_D<9>;
TRIOUT S:PIN131 = IDE_D<15>;
TRIOUT S:PIN45 = D<10>;
TRIOUT S:PIN44 = D<11>;
TRIOUT S:PIN43 = D<12>;
TRIOUT S:PIN41 = D<13>;
TRIOUT S:PIN40 = D<14>;
TRIOUT S:PIN39 = D<15>;
TRIOUT S:PIN52 = D<4>;
TRIOUT S:PIN51 = D<5>;
TRIOUT S:PIN50 = D<6>;
TRIOUT S:PIN49 = D<7>;
TRIOUT S:PIN48 = D<8>;
TRIOUT S:PIN46 = D<9>;
OUTPUT S:PIN20 = EA<18>;
OUTPUT S:PIN22 = EA<15>;
OUTPUT S:PIN21 = EA<16>;
OUTPUT S:PIN19 = EA<17>;
OUTPUT S:PIN32 = LED<0>;
OUTPUT S:PIN139 = LED<1>;
OUTPUT S:PIN134 = IDE_WR;
TRIOUT S:PIN30 = IDE_A<0>;
TRIOUT S:PIN140 = IDE_A<1>;
TRIOUT S:PIN142 = IDE_A<2>;
TRIOUT S:PIN133 = IDE_A<3>;
OUTPUT S:PIN135 = IDE_RD;
OUTPUT S:PIN68 = DRAM_CE;
OUTPUT S:PIN60 = FLASH_RD;
OUTPUT S:PIN76 = DRAM_RD;
OUTPUT S:PIN71 = PRAM_RD;
OUTPUT S:PIN64 = FLASH_WE;
OUTPUT S:PIN66 = DRAM_WE;
OUTPUT S:PIN69 = PRAM_WE;
OUTPUT S:PIN61 = FLASH_CE;
OUTPUT S:PIN5 = IDE0_CS0;
OUTPUT S:PIN4 = IDE0_CS1;
OUTPUT S:PIN3 = IDE1_CS0;
OUTPUT S:PIN2 = IDE1_CS1;
OUTPUT S:PIN138 = INT3;
OUTPUT S:PIN70 = PRAM_CE;
OUTPUT S:PIN93 = SLOE;
OUTPUT S:PIN75 = SLRD;
OUTPUT S:PIN74 = SLWR;
OUTPUT S:PIN88 = FIFOADR1;
OUTPUT S:PIN91 = FIFOADR0;

/* timing arc definitions */
A<2>_D<0>_delay: DELAY (ENABLE_HIGH) A<2> D<0>;
IDE_D<0>_D<0>_delay: DELAY (ENABLE_HIGH) IDE_D<0> D<0>;
IOSTRB_D<0>_delay: DELAY (ENABLE_HIGH) IOSTRB D<0>;
A<0>_D<0>_delay: DELAY (ENABLE_HIGH) A<0> D<0>;
FLAGB_D<0>_delay: DELAY (ENABLE_HIGH) FLAGB D<0>;
PB<0>_D<0>_delay: DELAY (ENABLE_HIGH) PB<0> D<0>;
PA0_D<0>_delay: DELAY (ENABLE_HIGH) PA0 D<0>;
A15_D<0>_delay: DELAY (ENABLE_HIGH) A15 D<0>;
A<3>_D<0>_delay: DELAY (ENABLE_HIGH) A<3> D<0>;
RW_D<0>_delay: DELAY (ENABLE_HIGH) RW D<0>;
A<1>_D<0>_delay: DELAY (ENABLE_HIGH) A<1> D<0>;
IOSTRB_D<10>_delay: DELAY (ENABLE_HIGH) IOSTRB D<10>;
RW_D<10>_delay: DELAY (ENABLE_HIGH) RW D<10>;
IDE_D<10>_D<10>_delay: DELAY (ENABLE_HIGH) IDE_D<10> D<10>;
A15_D<10>_delay: DELAY (ENABLE_HIGH) A15 D<10>;
A15_D<11>_delay: DELAY (ENABLE_HIGH) A15 D<11>;
IDE_D<11>_D<11>_delay: DELAY (ENABLE_HIGH) IDE_D<11> D<11>;
IOSTRB_D<11>_delay: DELAY (ENABLE_HIGH) IOSTRB D<11>;
RW_D<11>_delay: DELAY (ENABLE_HIGH) RW D<11>;
A15_D<12>_delay: DELAY (ENABLE_HIGH) A15 D<12>;
RW_D<12>_delay: DELAY (ENABLE_HIGH) RW D<12>;
IOSTRB_D<12>_delay: DELAY (ENABLE_HIGH) IOSTRB D<12>;
IDE_D<12>_D<12>_delay: DELAY (ENABLE_HIGH) IDE_D<12> D<12>;
A15_D<13>_delay: DELAY (ENABLE_HIGH) A15 D<13>;
IOSTRB_D<13>_delay: DELAY (ENABLE_HIGH) IOSTRB D<13>;
IDE_D<13>_D<13>_delay: DELAY (ENABLE_HIGH) IDE_D<13> D<13>;
RW_D<13>_delay: DELAY (ENABLE_HIGH) RW D<13>;
IOSTRB_D<14>_delay: DELAY (ENABLE_HIGH) IOSTRB D<14>;
A15_D<14>_delay: DELAY (ENABLE_HIGH) A15 D<14>;
RW_D<14>_delay: DELAY (ENABLE_HIGH) RW D<14>;
IDE_D<14>_D<14>_delay: DELAY (ENABLE_HIGH) IDE_D<14> D<14>;
A15_D<15>_delay: DELAY (ENABLE_HIGH) A15 D<15>;
IDE_D<15>_D<15>_delay: DELAY (ENABLE_HIGH) IDE_D<15> D<15>;
RW_D<15>_delay: DELAY (ENABLE_HIGH) RW D<15>;
IOSTRB_D<15>_delay: DELAY (ENABLE_HIGH) IOSTRB D<15>;
PB<1>_D<1>_delay: DELAY (ENABLE_HIGH) PB<1> D<1>;
PA1_D<1>_delay: DELAY (ENABLE_HIGH) PA1 D<1>;
IDE_D<1>_D<1>_delay: DELAY (ENABLE_HIGH) IDE_D<1> D<1>;
RW_D<1>_delay: DELAY (ENABLE_HIGH) RW D<1>;
FLAGC_D<1>_delay: DELAY (ENABLE_HIGH) FLAGC D<1>;
IOSTRB_D<1>_delay: DELAY (ENABLE_HIGH) IOSTRB D<1>;
A<1>_D<1>_delay: DELAY (ENABLE_HIGH) A<1> D<1>;
A<0>_D<1>_delay: DELAY (ENABLE_HIGH) A<0> D<1>;
A15_D<1>_delay: DELAY (ENABLE_HIGH) A15 D<1>;
A<3>_D<1>_delay: DELAY (ENABLE_HIGH) A<3> D<1>;
A<2>_D<1>_delay: DELAY (ENABLE_HIGH) A<2> D<1>;
RW_D<2>_delay: DELAY (ENABLE_HIGH) RW D<2>;
A<0>_D<2>_delay: DELAY (ENABLE_HIGH) A<0> D<2>;
A<1>_D<2>_delay: DELAY (ENABLE_HIGH) A<1> D<2>;
A<2>_D<2>_delay: DELAY (ENABLE_HIGH) A<2> D<2>;
A<3>_D<2>_delay: DELAY (ENABLE_HIGH) A<3> D<2>;
IOSTRB_D<2>_delay: DELAY (ENABLE_HIGH) IOSTRB D<2>;
IDE_D<2>_D<2>_delay: DELAY (ENABLE_HIGH) IDE_D<2> D<2>;
PB<2>_D<2>_delay: DELAY (ENABLE_HIGH) PB<2> D<2>;
A15_D<2>_delay: DELAY (ENABLE_HIGH) A15 D<2>;
IDE_D<3>_D<3>_delay: DELAY (ENABLE_HIGH) IDE_D<3> D<3>;
IOSTRB_D<3>_delay: DELAY (ENABLE_HIGH) IOSTRB D<3>;
RW_D<3>_delay: DELAY (ENABLE_HIGH) RW D<3>;
A<0>_D<3>_delay: DELAY (ENABLE_HIGH) A<0> D<3>;
A<1>_D<3>_delay: DELAY (ENABLE_HIGH) A<1> D<3>;
A<2>_D<3>_delay: DELAY (ENABLE_HIGH) A<2> D<3>;
A<3>_D<3>_delay: DELAY (ENABLE_HIGH) A<3> D<3>;
PB<3>_D<3>_delay: DELAY (ENABLE_HIGH) PB<3> D<3>;
A15_D<3>_delay: DELAY (ENABLE_HIGH) A15 D<3>;
PB<4>_D<4>_delay: DELAY (ENABLE_HIGH) PB<4> D<4>;
A15_D<4>_delay: DELAY (ENABLE_HIGH) A15 D<4>;
A<3>_D<4>_delay: DELAY (ENABLE_HIGH) A<3> D<4>;
A<2>_D<4>_delay: DELAY (ENABLE_HIGH) A<2> D<4>;
A<1>_D<4>_delay: DELAY (ENABLE_HIGH) A<1> D<4>;
A<0>_D<4>_delay: DELAY (ENABLE_HIGH) A<0> D<4>;
RW_D<4>_delay: DELAY (ENABLE_HIGH) RW D<4>;
IOSTRB_D<4>_delay: DELAY (ENABLE_HIGH) IOSTRB D<4>;
IDE_D<4>_D<4>_delay: DELAY (ENABLE_HIGH) IDE_D<4> D<4>;
A15_D<5>_delay: DELAY (ENABLE_HIGH) A15 D<5>;
A<3>_D<5>_delay: DELAY (ENABLE_HIGH) A<3> D<5>;
PB<5>_D<5>_delay: DELAY (ENABLE_HIGH) PB<5> D<5>;
A<2>_D<5>_delay: DELAY (ENABLE_HIGH) A<2> D<5>;
A<1>_D<5>_delay: DELAY (ENABLE_HIGH) A<1> D<5>;
A<0>_D<5>_delay: DELAY (ENABLE_HIGH) A<0> D<5>;
RW_D<5>_delay: DELAY (ENABLE_HIGH) RW D<5>;
IOSTRB_D<5>_delay: DELAY (ENABLE_HIGH) IOSTRB D<5>;
IDE_D<5>_D<5>_delay: DELAY (ENABLE_HIGH) IDE_D<5> D<5>;
A<2>_D<6>_delay: DELAY (ENABLE_HIGH) A<2> D<6>;
IDE_D<6>_D<6>_delay: DELAY (ENABLE_HIGH) IDE_D<6> D<6>;
IOSTRB_D<6>_delay: DELAY (ENABLE_HIGH) IOSTRB D<6>;
RW_D<6>_delay: DELAY (ENABLE_HIGH) RW D<6>;
A15_D<6>_delay: DELAY (ENABLE_HIGH) A15 D<6>;
A<3>_D<6>_delay: DELAY (ENABLE_HIGH) A<3> D<6>;
A<0>_D<6>_delay: DELAY (ENABLE_HIGH) A<0> D<6>;
A<1>_D<6>_delay: DELAY (ENABLE_HIGH) A<1> D<6>;
PB<6>_D<6>_delay: DELAY (ENABLE_HIGH) PB<6> D<6>;
A<1>_D<7>_delay: DELAY (ENABLE_HIGH) A<1> D<7>;
IDE_D<7>_D<7>_delay: DELAY (ENABLE_HIGH) IDE_D<7> D<7>;
PB<7>_D<7>_delay: DELAY (ENABLE_HIGH) PB<7> D<7>;
A<2>_D<7>_delay: DELAY (ENABLE_HIGH) A<2> D<7>;
A15_D<7>_delay: DELAY (ENABLE_HIGH) A15 D<7>;
A<3>_D<7>_delay: DELAY (ENABLE_HIGH) A<3> D<7>;
IOSTRB_D<7>_delay: DELAY (ENABLE_HIGH) IOSTRB D<7>;
A<0>_D<7>_delay: DELAY (ENABLE_HIGH) A<0> D<7>;
RW_D<7>_delay: DELAY (ENABLE_HIGH) RW D<7>;
A15_D<8>_delay: DELAY (ENABLE_HIGH) A15 D<8>;
IDE_D<8>_D<8>_delay: DELAY (ENABLE_HIGH) IDE_D<8> D<8>;
RW_D<8>_delay: DELAY (ENABLE_HIGH) RW D<8>;
IOSTRB_D<8>_delay: DELAY (ENABLE_HIGH) IOSTRB D<8>;
IDE_D<9>_D<9>_delay: DELAY (ENABLE_HIGH) IDE_D<9> D<9>;
RW_D<9>_delay: DELAY (ENABLE_HIGH) RW D<9>;
IOSTRB_D<9>_delay: DELAY (ENABLE_HIGH) IOSTRB D<9>;
A15_D<9>_delay: DELAY (ENABLE_HIGH) A15 D<9>;
DS_DRAM_CE_delay: DELAY DS DRAM_CE;
RW_DRAM_RD_delay: DELAY RW DRAM_RD;
MSTRB_DRAM_RD_delay: DELAY MSTRB DRAM_RD;
RW_DRAM_WE_delay: DELAY RW DRAM_WE;
MSTRB_DRAM_WE_delay: DELAY MSTRB DRAM_WE;
DS_FLASH_CE_delay: DELAY DS FLASH_CE;
MSTRB_FLASH_RD_delay: DELAY MSTRB FLASH_RD;
RW_FLASH_RD_delay: DELAY RW FLASH_RD;
MSTRB_FLASH_WE_delay: DELAY MSTRB FLASH_WE;
RW_FLASH_WE_delay: DELAY RW FLASH_WE;