my.mod

TMS3205402Verilog HDL源码

IS_D<9>_delay: DELAY (ENABLE_HIGH) IS D<9>;
IDE_D<9>_D<9>_delay: DELAY (ENABLE_HIGH) IDE_D<9> D<9>;
DS_DRAM_CE_delay: DELAY DS DRAM_CE;
MSTRB_DRAM_RD_delay: DELAY MSTRB DRAM_RD;
RW_DRAM_RD_delay: DELAY RW DRAM_RD;
RW_DRAM_WE_delay: DELAY RW DRAM_WE;
MSTRB_DRAM_WE_delay: DELAY MSTRB DRAM_WE;
A<0>_FIFOADR0_delay: DELAY A<0> FIFOADR0;
A<1>_FIFOADR1_delay: DELAY A<1> FIFOADR1;
DS_FLASH_CE_delay: DELAY DS FLASH_CE;
MSTRB_FLASH_RD_delay: DELAY MSTRB FLASH_RD;
RW_FLASH_RD_delay: DELAY RW FLASH_RD;
RW_FLASH_WE_delay: DELAY RW FLASH_WE;
MSTRB_FLASH_WE_delay: DELAY MSTRB FLASH_WE;
A15_IDE0_CS0_delay: DELAY A15 IDE0_CS0;
IS_IDE0_CS0_delay: DELAY IS IDE0_CS0;
A14_IDE0_CS0_delay: DELAY A14 IDE0_CS0;
IS_IDE0_CS1_delay: DELAY IS IDE0_CS1;
A15_IDE0_CS1_delay: DELAY A15 IDE0_CS1;
A14_IDE0_CS1_delay: DELAY A14 IDE0_CS1;
A14_IDE1_CS0_delay: DELAY A14 IDE1_CS0;
A15_IDE1_CS0_delay: DELAY A15 IDE1_CS0;
IS_IDE1_CS0_delay: DELAY IS IDE1_CS0;
A14_IDE1_CS1_delay: DELAY A14 IDE1_CS1;
A15_IDE1_CS1_delay: DELAY A15 IDE1_CS1;
IS_IDE1_CS1_delay: DELAY IS IDE1_CS1;
A<0>_IDE_A<0>_delay: DELAY A<0> IDE_A<0>;
A<1>_IDE_A<1>_delay: DELAY A<1> IDE_A<1>;
A<2>_IDE_A<2>_delay: DELAY A<2> IDE_A<2>;
A<3>_IDE_A<3>_delay: DELAY A<3> IDE_A<3>;
D<0>_IDE_D<0>_delay: DELAY (ENABLE_HIGH) D<0> IDE_D<0>;
RW_IDE_D<0>_delay: DELAY (ENABLE_HIGH) RW IDE_D<0>;
IS_IDE_D<0>_delay: DELAY (ENABLE_HIGH) IS IDE_D<0>;
A15_IDE_D<0>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<0>;
IOSTRB_IDE_D<0>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<0>;
IOSTRB_IDE_D<10>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<10>;
RW_IDE_D<10>_delay: DELAY (ENABLE_HIGH) RW IDE_D<10>;
D<10>_IDE_D<10>_delay: DELAY (ENABLE_HIGH) D<10> IDE_D<10>;
A15_IDE_D<10>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<10>;
IS_IDE_D<10>_delay: DELAY (ENABLE_HIGH) IS IDE_D<10>;
A15_IDE_D<11>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<11>;
D<11>_IDE_D<11>_delay: DELAY (ENABLE_HIGH) D<11> IDE_D<11>;
IOSTRB_IDE_D<11>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<11>;
RW_IDE_D<11>_delay: DELAY (ENABLE_HIGH) RW IDE_D<11>;
IS_IDE_D<11>_delay: DELAY (ENABLE_HIGH) IS IDE_D<11>;
D<12>_IDE_D<12>_delay: DELAY (ENABLE_HIGH) D<12> IDE_D<12>;
RW_IDE_D<12>_delay: DELAY (ENABLE_HIGH) RW IDE_D<12>;
IS_IDE_D<12>_delay: DELAY (ENABLE_HIGH) IS IDE_D<12>;
A15_IDE_D<12>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<12>;
IOSTRB_IDE_D<12>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<12>;
RW_IDE_D<13>_delay: DELAY (ENABLE_HIGH) RW IDE_D<13>;
IOSTRB_IDE_D<13>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<13>;
A15_IDE_D<13>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<13>;
IS_IDE_D<13>_delay: DELAY (ENABLE_HIGH) IS IDE_D<13>;
D<13>_IDE_D<13>_delay: DELAY (ENABLE_HIGH) D<13> IDE_D<13>;
D<14>_IDE_D<14>_delay: DELAY (ENABLE_HIGH) D<14> IDE_D<14>;
IS_IDE_D<14>_delay: DELAY (ENABLE_HIGH) IS IDE_D<14>;
RW_IDE_D<14>_delay: DELAY (ENABLE_HIGH) RW IDE_D<14>;
IOSTRB_IDE_D<14>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<14>;
A15_IDE_D<14>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<14>;
IOSTRB_IDE_D<15>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<15>;
A15_IDE_D<15>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<15>;
D<15>_IDE_D<15>_delay: DELAY (ENABLE_HIGH) D<15> IDE_D<15>;
IS_IDE_D<15>_delay: DELAY (ENABLE_HIGH) IS IDE_D<15>;
RW_IDE_D<15>_delay: DELAY (ENABLE_HIGH) RW IDE_D<15>;
RW_IDE_D<1>_delay: DELAY (ENABLE_HIGH) RW IDE_D<1>;
IOSTRB_IDE_D<1>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<1>;
A15_IDE_D<1>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<1>;
IS_IDE_D<1>_delay: DELAY (ENABLE_HIGH) IS IDE_D<1>;
D<1>_IDE_D<1>_delay: DELAY (ENABLE_HIGH) D<1> IDE_D<1>;
RW_IDE_D<2>_delay: DELAY (ENABLE_HIGH) RW IDE_D<2>;
IOSTRB_IDE_D<2>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<2>;
A15_IDE_D<2>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<2>;
IS_IDE_D<2>_delay: DELAY (ENABLE_HIGH) IS IDE_D<2>;
D<2>_IDE_D<2>_delay: DELAY (ENABLE_HIGH) D<2> IDE_D<2>;
RW_IDE_D<3>_delay: DELAY (ENABLE_HIGH) RW IDE_D<3>;
IOSTRB_IDE_D<3>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<3>;
A15_IDE_D<3>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<3>;
IS_IDE_D<3>_delay: DELAY (ENABLE_HIGH) IS IDE_D<3>;
D<3>_IDE_D<3>_delay: DELAY (ENABLE_HIGH) D<3> IDE_D<3>;
D<4>_IDE_D<4>_delay: DELAY (ENABLE_HIGH) D<4> IDE_D<4>;
RW_IDE_D<4>_delay: DELAY (ENABLE_HIGH) RW IDE_D<4>;
IOSTRB_IDE_D<4>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<4>;
A15_IDE_D<4>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<4>;
IS_IDE_D<4>_delay: DELAY (ENABLE_HIGH) IS IDE_D<4>;
RW_IDE_D<5>_delay: DELAY (ENABLE_HIGH) RW IDE_D<5>;
IOSTRB_IDE_D<5>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<5>;
A15_IDE_D<5>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<5>;
IS_IDE_D<5>_delay: DELAY (ENABLE_HIGH) IS IDE_D<5>;
D<5>_IDE_D<5>_delay: DELAY (ENABLE_HIGH) D<5> IDE_D<5>;
RW_IDE_D<6>_delay: DELAY (ENABLE_HIGH) RW IDE_D<6>;
IOSTRB_IDE_D<6>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<6>;
IS_IDE_D<6>_delay: DELAY (ENABLE_HIGH) IS IDE_D<6>;
D<6>_IDE_D<6>_delay: DELAY (ENABLE_HIGH) D<6> IDE_D<6>;
A15_IDE_D<6>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<6>;
IOSTRB_IDE_D<7>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<7>;
A15_IDE_D<7>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<7>;
IS_IDE_D<7>_delay: DELAY (ENABLE_HIGH) IS IDE_D<7>;
RW_IDE_D<7>_delay: DELAY (ENABLE_HIGH) RW IDE_D<7>;
D<7>_IDE_D<7>_delay: DELAY (ENABLE_HIGH) D<7> IDE_D<7>;
IOSTRB_IDE_D<8>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<8>;
A15_IDE_D<8>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<8>;
IS_IDE_D<8>_delay: DELAY (ENABLE_HIGH) IS IDE_D<8>;
D<8>_IDE_D<8>_delay: DELAY (ENABLE_HIGH) D<8> IDE_D<8>;
RW_IDE_D<8>_delay: DELAY (ENABLE_HIGH) RW IDE_D<8>;
IOSTRB_IDE_D<9>_delay: DELAY (ENABLE_HIGH) IOSTRB IDE_D<9>;
A15_IDE_D<9>_delay: DELAY (ENABLE_HIGH) A15 IDE_D<9>;
D<9>_IDE_D<9>_delay: DELAY (ENABLE_HIGH) D<9> IDE_D<9>;
RW_IDE_D<9>_delay: DELAY (ENABLE_HIGH) RW IDE_D<9>;
IS_IDE_D<9>_delay: DELAY (ENABLE_HIGH) IS IDE_D<9>;
RW_IDE_RD_delay: DELAY RW IDE_RD;
IS_IDE_RD_delay: DELAY IS IDE_RD;
A15_IDE_RD_delay: DELAY A15 IDE_RD;
IOSTRB_IDE_RD_delay: DELAY IOSTRB IDE_RD;
IOSTRB_IDE_WR_delay: DELAY IOSTRB IDE_WR;
RW_IDE_WR_delay: DELAY RW IDE_WR;
A15_IDE_WR_delay: DELAY A15 IDE_WR;
IS_IDE_WR_delay: DELAY IS IDE_WR;
PA3_INT3_delay: DELAY PA3 INT3;
PS_PRAM_CE_delay: DELAY PS PRAM_CE;
RW_PRAM_RD_delay: DELAY RW PRAM_RD;
MSTRB_PRAM_RD_delay: DELAY MSTRB PRAM_RD;
RW_PRAM_WE_delay: DELAY RW PRAM_WE;
MSTRB_PRAM_WE_delay: DELAY MSTRB PRAM_WE;
IS_SLCS_delay: DELAY IS SLCS;
A15_SLCS_delay: DELAY A15 SLCS;
A14_SLCS_delay: DELAY A14 SLCS;
A15_SLOE_delay: DELAY A15 SLOE;
IS_SLOE_delay: DELAY IS SLOE;
RW_SLOE_delay: DELAY RW SLOE;
A14_SLOE_delay: DELAY A14 SLOE;
A15_SLRD_delay: DELAY A15 SLRD;
IS_SLRD_delay: DELAY IS SLRD;
IOSTRB_SLRD_delay: DELAY IOSTRB SLRD;
A14_SLRD_delay: DELAY A14 SLRD;
RW_SLRD_delay: DELAY RW SLRD;
A15_SLWR_delay: DELAY A15 SLWR;
IS_SLWR_delay: DELAY IS SLWR;
IOSTRB_SLWR_delay: DELAY IOSTRB SLWR;
RW_SLWR_delay: DELAY RW SLWR;
A14_SLWR_delay: DELAY A14 SLWR;
IOSTRB_D<4>_delay: DELAY (ENABLE_HIGH) IOSTRB D<4>;
IOSTRB_D<0>_delay: DELAY (ENABLE_HIGH) IOSTRB D<0>;
IOSTRB_D<1>_delay: DELAY (ENABLE_HIGH) IOSTRB D<1>;
IOSTRB_D<2>_delay: DELAY (ENABLE_HIGH) IOSTRB D<2>;
IOSTRB_D<3>_delay: DELAY (ENABLE_HIGH) IOSTRB D<3>;
IOSTRB_EA<19>_delay: DELAY IOSTRB EA<19>;
IOSTRB_EA<15>_delay: DELAY IOSTRB EA<15>;
IOSTRB_EA<16>_delay: DELAY IOSTRB EA<16>;
IOSTRB_EA<17>_delay: DELAY IOSTRB EA<17>;
IOSTRB_EA<18>_delay: DELAY IOSTRB EA<18>;
IOSTRB_LED<0>_delay: DELAY IOSTRB LED<0>;
IOSTRB_LED<1>_delay: DELAY IOSTRB LED<1>;
IOSTRB_DRAM_CE_delay: DELAY IOSTRB DRAM_CE;
IOSTRB_FLASH_CE_delay: DELAY IOSTRB FLASH_CE;
IOSTRB_IDE0_CS0_delay: DELAY IOSTRB IDE0_CS0;
IOSTRB_IDE0_CS1_delay: DELAY IOSTRB IDE0_CS1;
IOSTRB_IDE1_CS0_delay: DELAY IOSTRB IDE1_CS0;
IOSTRB_IDE1_CS1_delay: DELAY IOSTRB IDE1_CS1;
RW_D<4>_delay: DELAY (ENABLE_HIGH) RW D<4>;
RW_D<0>_delay: DELAY (ENABLE_HIGH) RW D<0>;
RW_D<1>_delay: DELAY (ENABLE_HIGH) RW D<1>;
RW_D<2>_delay: DELAY (ENABLE_HIGH) RW D<2>;
RW_D<3>_delay: DELAY (ENABLE_HIGH) RW D<3>;
RW_EA<19>_delay: DELAY RW EA<19>;
RW_EA<15>_delay: DELAY RW EA<15>;
RW_EA<16>_delay: DELAY RW EA<16>;
RW_EA<17>_delay: DELAY RW EA<17>;
RW_EA<18>_delay: DELAY RW EA<18>;
RW_LED<0>_delay: DELAY RW LED<0>;
RW_LED<1>_delay: DELAY RW LED<1>;
RW_DRAM_CE_delay: DELAY RW DRAM_CE;
RW_FLASH_CE_delay: DELAY RW FLASH_CE;
RW_IDE0_CS0_delay: DELAY RW IDE0_CS0;
RW_IDE0_CS1_delay: DELAY RW IDE0_CS1;
RW_IDE1_CS0_delay: DELAY RW IDE1_CS0;
RW_IDE1_CS1_delay: DELAY RW IDE1_CS1;

/* timing check arc definitions */
A14_IOSTRB_setup: SETUP(POSEDGE) A14 IOSTRB;
A15_IOSTRB_setup: SETUP(POSEDGE) A15 IOSTRB;
A<0>_IOSTRB_setup: SETUP(POSEDGE) A<0> IOSTRB;
A<1>_IOSTRB_setup: SETUP(POSEDGE) A<1> IOSTRB;
D<0>_IOSTRB_setup: SETUP(POSEDGE) D<0> IOSTRB;
D<1>_IOSTRB_setup: SETUP(POSEDGE) D<1> IOSTRB;
D<2>_IOSTRB_setup: SETUP(POSEDGE) D<2> IOSTRB;
D<3>_IOSTRB_setup: SETUP(POSEDGE) D<3> IOSTRB;
D<4>_IOSTRB_setup: SETUP(POSEDGE) D<4> IOSTRB;
IS_IOSTRB_setup: SETUP(POSEDGE) IS IOSTRB;
A14_IOSTRB_hold: HOLD(POSEDGE) A14 IOSTRB;
A15_IOSTRB_hold: HOLD(POSEDGE) A15 IOSTRB;
A<0>_IOSTRB_hold: HOLD(POSEDGE) A<0> IOSTRB;
A<1>_IOSTRB_hold: HOLD(POSEDGE) A<1> IOSTRB;
D<0>_IOSTRB_hold: HOLD(POSEDGE) D<0> IOSTRB;
D<1>_IOSTRB_hold: HOLD(POSEDGE) D<1> IOSTRB;
D<2>_IOSTRB_hold: HOLD(POSEDGE) D<2> IOSTRB;
D<3>_IOSTRB_hold: HOLD(POSEDGE) D<3> IOSTRB;
D<4>_IOSTRB_hold: HOLD(POSEDGE) D<4> IOSTRB;
IS_IOSTRB_hold: HOLD(POSEDGE) IS IOSTRB;
A14_RW_setup: SETUP(POSEDGE) A14 RW;
A15_RW_setup: SETUP(POSEDGE) A15 RW;
A<0>_RW_setup: SETUP(POSEDGE) A<0> RW;
A<1>_RW_setup: SETUP(POSEDGE) A<1> RW;
D<0>_RW_setup: SETUP(POSEDGE) D<0> RW;
D<1>_RW_setup: SETUP(POSEDGE) D<1> RW;
D<2>_RW_setup: SETUP(POSEDGE) D<2> RW;
D<3>_RW_setup: SETUP(POSEDGE) D<3> RW;
D<4>_RW_setup: SETUP(POSEDGE) D<4> RW;
IS_RW_setup: SETUP(POSEDGE) IS RW;
A14_RW_hold: HOLD(POSEDGE) A14 RW;
A15_RW_hold: HOLD(POSEDGE) A15 RW;
A<0>_RW_hold: HOLD(POSEDGE) A<0> RW;
A<1>_RW_hold: HOLD(POSEDGE) A<1> RW;
D<0>_RW_hold: HOLD(POSEDGE) D<0> RW;
D<1>_RW_hold: HOLD(POSEDGE) D<1> RW;
D<2>_RW_hold: HOLD(POSEDGE) D<2> RW;
D<3>_RW_hold: HOLD(POSEDGE) D<3> RW;
D<4>_RW_hold: HOLD(POSEDGE) D<4> RW;
IS_RW_hold: HOLD(POSEDGE) IS RW;

ENDMODEL