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assign IDE_D_I[0] = D[0].PIN;
assign IDE_D[0] = IDE_D_OE[0] ? IDE_D_I[0] : 1'bZ;
assign IDE_D_OE[0] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[1] = D[1].PIN;
assign IDE_D[1] = IDE_D_OE[1] ? IDE_D_I[1] : 1'bZ;
assign IDE_D_OE[1] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[2] = D[2].PIN;
assign IDE_D[2] = IDE_D_OE[2] ? IDE_D_I[2] : 1'bZ;
assign IDE_D_OE[2] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[3] = D[3].PIN;
assign IDE_D[3] = IDE_D_OE[3] ? IDE_D_I[3] : 1'bZ;
assign IDE_D_OE[3] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[4] = D[4].PIN;
assign IDE_D[4] = IDE_D_OE[4] ? IDE_D_I[4] : 1'bZ;
assign IDE_D_OE[4] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[5] = D[5].PIN;
assign IDE_D[5] = IDE_D_OE[5] ? IDE_D_I[5] : 1'bZ;
assign IDE_D_OE[5] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[6] = D[6].PIN;
assign IDE_D[6] = IDE_D_OE[6] ? IDE_D_I[6] : 1'bZ;
assign IDE_D_OE[6] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[7] = D[7].PIN;
assign IDE_D[7] = IDE_D_OE[7] ? IDE_D_I[7] : 1'bZ;
assign IDE_D_OE[7] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[8] = D[8].PIN;
assign IDE_D[8] = IDE_D_OE[8] ? IDE_D_I[8] : 1'bZ;
assign IDE_D_OE[8] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[9] = D[9].PIN;
assign IDE_D[9] = IDE_D_OE[9] ? IDE_D_I[9] : 1'bZ;
assign IDE_D_OE[9] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[10] = D[10].PIN;
assign IDE_D[10] = IDE_D_OE[10] ? IDE_D_I[10] : 1'bZ;
assign IDE_D_OE[10] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[11] = D[11].PIN;
assign IDE_D[11] = IDE_D_OE[11] ? IDE_D_I[11] : 1'bZ;
assign IDE_D_OE[11] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[12] = D[12].PIN;
assign IDE_D[12] = IDE_D_OE[12] ? IDE_D_I[12] : 1'bZ;
assign IDE_D_OE[12] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[13] = D[13].PIN;
assign IDE_D[13] = IDE_D_OE[13] ? IDE_D_I[13] : 1'bZ;
assign IDE_D_OE[13] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[14] = D[14].PIN;
assign IDE_D[14] = IDE_D_OE[14] ? IDE_D_I[14] : 1'bZ;
assign IDE_D_OE[14] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_D_I[15] = D[15].PIN;
assign IDE_D[15] = IDE_D_OE[15] ? IDE_D_I[15] : 1'bZ;
assign IDE_D_OE[15] = (!A15 && !IS && !RW && !IOSTRB);
assign IDE_RD = !((!A15 && !IS && RW && !IOSTRB));
assign IDE_WR = !((!A15 && !IS && !RW && !IOSTRB));
assign INT3 = PA3;
FDCPE FDCPE_LED0 (LED0,D[0].PIN,LED0_C,! CPLD_RESET,1'b0,LED0_CE);
assign LED0_C = !((!RW && !IOSTRB));
assign LED0_CE = (!A[2] && A[1] && !A[0] && A15 && !IS && !A14);
assign LED1 = PA7;
assign PB_I[0] = D[0].PIN;
assign PB[0] = PB_OE[0] ? PB_I[0] : 1'bZ;
assign PB_OE[0] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[1] = D[1].PIN;
assign PB[1] = PB_OE[1] ? PB_I[1] : 1'bZ;
assign PB_OE[1] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[2] = D[2].PIN;
assign PB[2] = PB_OE[2] ? PB_I[2] : 1'bZ;
assign PB_OE[2] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[3] = D[3].PIN;
assign PB[3] = PB_OE[3] ? PB_I[3] : 1'bZ;
assign PB_OE[3] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[4] = D[4].PIN;
assign PB[4] = PB_OE[4] ? PB_I[4] : 1'bZ;
assign PB_OE[4] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[5] = D[5].PIN;
assign PB[5] = PB_OE[5] ? PB_I[5] : 1'bZ;
assign PB_OE[5] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[6] = D[6].PIN;
assign PB[6] = PB_OE[6] ? PB_I[6] : 1'bZ;
assign PB_OE[6] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PB_I[7] = D[7].PIN;
assign PB[7] = PB_OE[7] ? PB_I[7] : 1'bZ;
assign PB_OE[7] = (A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB);
assign PKTEND = 1'b1;
assign PRAM_CE = PS;
assign PRAM_RD = !((RW && !MSTRB));
assign PRAM_WE = !((!RW && !MSTRB));
assign SLOE = !((A[3] && !A[2] && A15 && !IS && A14 && RW));
assign SLRD = !((A[3] && !A[2] && A15 && !IS && A14 && RW && !IOSTRB));
assign SLWR = !((A[3] && !A[2] && A15 && !IS && A14 && !RW && !IOSTRB));
FDCPE FDCPE_ide_num (ide_num,D[0].PIN,ide_num_C,1'b0,! CPLD_RESET,ide_num_CE);
assign ide_num_C = !((!RW && !IOSTRB));
assign ide_num_CE = (!A[2] && !A[1] && A[0] && A15 && !IS && !A14);
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 IDE1_CS1 74 SLWR
3 IDE1_CS0 75 SLRD
4 IDE0_CS1 76 EA<19>
5 IDE0_CS0 77 KPR
6 CARD0_RST 78 KPR
7 CARD0_CLK 79 KPR
8 VCC 80 DRAM_RD2
9 CARD0_FLG 81 KPR
10 CARD0_LED 82 KPR
11 CARD0_DATA 83 KPR
12 IOSTRB 84 VCC
13 MSTRB 85 DRAM_WE3
14 RW 86 PA7
15 IS 87 PKTEND
16 DS 88 FIFOADR1
17 PS 89 GND
18 GND 90 GND
19 EA<17> 91 FIFOADR0
20 EA<18> 92 PA3
21 EA<16> 93 SLOE
22 EA<15> 94 PA1
23 CARD1_DATA 95 PA0
24 CARD1_LED 96 FLAGC
25 CARD1_FLG 97 FLAGB
26 CARD1_CLK 98 KPR
27 CARD1_RST 99 GND
28 KPR 100 PB<7>
29 GND 101 PB<6>
30 IDE_A<0> 102 PB<5>
31 A<3> 103 PB<4>
32 LED0 104 PB<3>
33 A<2> 105 PB<2>
34 A<1> 106 PB<1>
35 A<0> 107 PB<0>
36 GND 108 GND
37 VCC 109 VCC
38 GCLK 110 KPR
39 D<15> 111 KPR
40 D<14> 112 KPR
41 D<13> 113 IDE_D<8>
42 VCC 114 GND
43 D<12> 115 IDE_D<7>
44 D<11> 116 IDE_D<9>
45 D<10> 117 IDE_D<6>
46 D<9> 118 IDE_D<10>
47 GND 119 IDE_D<5>
48 D<8> 120 IDE_D<11>
49 D<7> 121 IDE_D<4>
50 D<6> 122 TDO
51 D<5> 123 GND
52 D<4> 124 IDE_D<12>
53 D<3> 125 IDE_D<3>
54 D<2> 126 IDE_D<13>
55 VCC 127 VCC
56 D<1> 128 IDE_D<2>
57 D<0> 129 IDE_D<14>
58 A14 130 IDE_D<1>
59 A15 131 IDE_D<15>
60 FLASH_RD 132 IDE_D<0>
61 FLASH_CE 133 IDE_A<3>
62 GND 134 IDE_WR
63 TDI 135 IDE_RD
64 FLASH_WE 136 A<4>
65 TMS 137 KPR
66 KPR 138 INT3
67 TCK 139 LED1
68 DRAM_CE 140 IDE_A<1>
69 PRAM_WE 141 VCC
70 PRAM_CE 142 IDE_A<2>
71 PRAM_RD 143 CPLD_RESET
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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