my.rpt

TMS3205402Verilog HDL源码

PB<2>                 2       0     0   3     FB8_17  105   I/O     I/O
(unused)              0       0     0   5     FB8_18        (b)     

Signals Used by Logic in Function Block
  1: A14                6: D<0>.PIN          11: D<6>.PIN 
  2: A15                7: D<2>.PIN          12: IOSTRB 
  3: A<0>               8: D<3>.PIN          13: IS 
  4: A<2>               9: D<4>.PIN          14: D<7>.PIN 
  5: A<3>              10: D<5>.PIN          15: RW 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
FIFOADR0             ..X..................................... 1
SLOE                 XX.XX.......X.X......................... 6
PB<6>                XX.XX.....XXX.X......................... 8
PB<7>                XX.XX......XXXX......................... 8
PB<4>                XX.XX...X..XX.X......................... 8
PB<5>                XX.XX....X.XX.X......................... 8
PB<3>                XX.XX..X...XX.X......................... 8
PB<0>                XX.XXX.....XX.X......................... 8
PB<2>                XX.XX.X....XX.X......................... 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE FDCPE_CARD02 (CARD0[2],D[2].PIN,CARD0_C[2],! CPLD_RESET,1'b0,CARD0_CE[2]);
assign CARD0_C[2] = !((!RW && !IOSTRB));
assign CARD0_CE[2] = (A[2] && !A[1] && !A[0] && !CARD_NUM && A15 && !IS && 
	!A14);


assign CARD0_CLK = (CARD0[2] && COUNT[3]);

FDCPE FDCPE_CARD0_DATA (CARD0_DATA_I,D[0].PIN,CARD0_DATA_C,! CPLD_RESET,1'b0,CARD0_DATA_CE);
assign CARD0_DATA_C = !((!RW && !IOSTRB));
assign CARD0_DATA_CE = (A[2] && !A[1] && !A[0] && !CARD_NUM && A15 && !IS && 
	!A14);
assign CARD0_DATA = CARD0_DATA_OE ? CARD0_DATA_I : 1'bZ;
assign CARD0_DATA_OE = !CARD0_DATA;

FDCPE FDCPE_CARD0_LED (CARD0_LED,D[1].PIN,CARD0_LED_C,! CPLD_RESET,1'b0,CARD0_LED_CE);
assign CARD0_LED_C = !((!RW && !IOSTRB));
assign CARD0_LED_CE = (A[2] && !A[1] && !A[0] && !CARD_NUM && A15 && !IS && 
	!A14);

FDCPE FDCPE_CARD0_RST (CARD0_RST,D[3].PIN,CARD0_RST_C,! CPLD_RESET,1'b0,CARD0_RST_CE);
assign CARD0_RST_C = !((!RW && !IOSTRB));
assign CARD0_RST_CE = (A[2] && !A[1] && !A[0] && !CARD_NUM && A15 && !IS && 
	!A14);

FDCPE FDCPE_CARD12 (CARD1[2],D[2].PIN,CARD1_C[2],! CPLD_RESET,1'b0,CARD1_CE[2]);
assign CARD1_C[2] = !((!RW && !IOSTRB));
assign CARD1_CE[2] = (A[2] && !A[1] && !A[0] && CARD_NUM && A15 && !IS && 
	!A14);


assign CARD1_CLK = (CARD1[2] && COUNT[3]);

FDCPE FDCPE_CARD1_DATA (CARD1_DATA_I,D[0].PIN,CARD1_DATA_C,! CPLD_RESET,1'b0,CARD1_DATA_CE);
assign CARD1_DATA_C = !((!RW && !IOSTRB));
assign CARD1_DATA_CE = (A[2] && !A[1] && !A[0] && CARD_NUM && A15 && !IS && 
	!A14);
assign CARD1_DATA = CARD1_DATA_OE ? CARD1_DATA_I : 1'bZ;
assign CARD1_DATA_OE = !CARD1_DATA;

FDCPE FDCPE_CARD1_LED (CARD1_LED,D[1].PIN,CARD1_LED_C,! CPLD_RESET,1'b0,CARD1_LED_CE);
assign CARD1_LED_C = !((!RW && !IOSTRB));
assign CARD1_LED_CE = (A[2] && !A[1] && !A[0] && CARD_NUM && A15 && !IS && 
	!A14);

FDCPE FDCPE_CARD1_RST (CARD1_RST,D[3].PIN,CARD1_RST_C,! CPLD_RESET,1'b0,CARD1_RST_CE);
assign CARD1_RST_C = !((!RW && !IOSTRB));
assign CARD1_RST_CE = (A[2] && !A[1] && !A[0] && CARD_NUM && A15 && !IS && 
	!A14);

FDCPE FDCPE_CARD_NUM (CARD_NUM,D[0].PIN,CARD_NUM_C,! CPLD_RESET,1'b0,CARD_NUM_CE);
assign CARD_NUM_C = !((!RW && !IOSTRB));
assign CARD_NUM_CE = (A[2] && !A[1] && A[0] && A15 && !IS && !A14);

FTCPE FTCPE_COUNT0 (COUNT[0],1'b1,GCLK,! CPLD_RESET,1'b0);

FTCPE FTCPE_COUNT1 (COUNT[1],COUNT[0],GCLK,! CPLD_RESET,1'b0);

FTCPE FTCPE_COUNT2 (COUNT[2],COUNT_T[2],GCLK,! CPLD_RESET,1'b0);
assign COUNT_T[2] = (COUNT[0] && COUNT[1]);

FTCPE FTCPE_COUNT3 (COUNT[3],COUNT_T[3],GCLK,! CPLD_RESET,1'b0);
assign COUNT_T[3] = (COUNT[0] && COUNT[1] && COUNT[2]);


assign D_I[0] = !(((DRAM_CE_OBUF.EXP)
	|| (!A15 && !IS && !IDE_D[0].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[0].PIN)
	|| (!A[3] && A[2] && A15 && !IS && A14 && !PA0)
	|| (!A[3] && !A[2] && A15 && !IS && A14 && !FLAGB)));
assign D[0] = D_OE[0] ? D_I[0] : 1'bZ;
assign D_OE[0] = (RW && !IOSTRB);


assign D_I[1] = !(((EXP10_.EXP)
	|| (!A15 && !IS && !IDE_D[1].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[1].PIN)
	|| (!A[3] && A[2] && A15 && !IS && A14 && !PA1)
	|| (!A[3] && !A[2] && A15 && !IS && A14 && !FLAGC)));
assign D[1] = D_OE[1] ? D_I[1] : 1'bZ;
assign D_OE[1] = (RW && !IOSTRB);


assign D_I[2] = !(((!A15 && !IS && !IDE_D[2].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[2].PIN)
	|| (!A[2] && !A[1] && !A[0] && !EA[17] && A15 && !IS && !A14)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[2] = D_OE[2] ? D_I[2] : 1'bZ;
assign D_OE[2] = (RW && !IOSTRB);


assign D_I[3] = !(((!A15 && !IS && !IDE_D[3].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[3].PIN)
	|| (!A[2] && !A[1] && !A[0] && !EA[18] && A15 && !IS && !A14)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[3] = D_OE[3] ? D_I[3] : 1'bZ;
assign D_OE[3] = (RW && !IOSTRB);


assign D_I[4] = !(((!A15 && !IS && !IDE_D[4].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[4].PIN)
	|| (!A[2] && !A[1] && !A[0] && !EA[19] && A15 && !IS && !A14)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[4] = D_OE[4] ? D_I[4] : 1'bZ;
assign D_OE[4] = (RW && !IOSTRB);


assign D_I[5] = !(((!A15 && !IS && !IDE_D[5].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[5].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[5] = D_OE[5] ? D_I[5] : 1'bZ;
assign D_OE[5] = (RW && !IOSTRB);


assign D_I[6] = !(((!A15 && !IS && !IDE_D[6].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[6].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[6] = D_OE[6] ? D_I[6] : 1'bZ;
assign D_OE[6] = (RW && !IOSTRB);


assign D_I[7] = !(((!A15 && !IS && !IDE_D[7].PIN)
	|| (A[3] && !A[2] && A15 && !IS && A14 && !PB[7].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[7] = D_OE[7] ? D_I[7] : 1'bZ;
assign D_OE[7] = (RW && !IOSTRB);


assign D_I[8] = !(((!A15 && !IS && !IDE_D[8].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[8] = D_OE[8] ? D_I[8] : 1'bZ;
assign D_OE[8] = (RW && !IOSTRB);


assign D_I[9] = !(((!A15 && !IS && !IDE_D[9].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[9] = D_OE[9] ? D_I[9] : 1'bZ;
assign D_OE[9] = (RW && !IOSTRB);


assign D_I[10] = !(((!A15 && !IS && !IDE_D[10].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[10] = D_OE[10] ? D_I[10] : 1'bZ;
assign D_OE[10] = (RW && !IOSTRB);


assign D_I[11] = !(((!A15 && !IS && !IDE_D[11].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[11] = D_OE[11] ? D_I[11] : 1'bZ;
assign D_OE[11] = (RW && !IOSTRB);


assign D_I[12] = !(((!A15 && !IS && !IDE_D[12].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[12] = D_OE[12] ? D_I[12] : 1'bZ;
assign D_OE[12] = (RW && !IOSTRB);


assign D_I[13] = !(((!A15 && !IS && !IDE_D[13].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[13] = D_OE[13] ? D_I[13] : 1'bZ;
assign D_OE[13] = (RW && !IOSTRB);


assign D_I[14] = !(((!A15 && !IS && !IDE_D[14].PIN)
	|| (A[4] && A[3] && A[2] && A[1] && A[0] && A15 && !IS && 
	A14)));
assign D[14] = D_OE[14] ? D_I[14] : 1'bZ;
assign D_OE[14] = (RW && !IOSTRB);


assign D_I[15] = !((!A15 && !IS && !IDE_D[15].PIN));
assign D[15] = D_OE[15] ? D_I[15] : 1'bZ;
assign D_OE[15] = (RW && !IOSTRB);


assign DRAM_CE = !((EA[19] && !DS));


assign DRAM_RD2 = !((RW && !MSTRB));


assign DRAM_WE3 = !((!RW && !MSTRB));

FDCPE FDCPE_EA15 (EA[15],D[0].PIN,EA_C[15],! CPLD_RESET,1'b0,EA_CE[15]);
assign EA_C[15] = !((!RW && !IOSTRB));
assign EA_CE[15] = (!A[2] && !A[1] && !A[0] && A15 && !IS && !A14);

FDCPE FDCPE_EA16 (EA[16],D[1].PIN,EA_C[16],! CPLD_RESET,1'b0,EA_CE[16]);
assign EA_C[16] = !((!RW && !IOSTRB));
assign EA_CE[16] = (!A[2] && !A[1] && !A[0] && A15 && !IS && !A14);

FDCPE FDCPE_EA17 (EA[17],D[2].PIN,EA_C[17],! CPLD_RESET,1'b0,EA_CE[17]);
assign EA_C[17] = !((!RW && !IOSTRB));
assign EA_CE[17] = (!A[2] && !A[1] && !A[0] && A15 && !IS && !A14);

FDCPE FDCPE_EA18 (EA[18],D[3].PIN,EA_C[18],! CPLD_RESET,1'b0,EA_CE[18]);
assign EA_C[18] = !((!RW && !IOSTRB));
assign EA_CE[18] = (!A[2] && !A[1] && !A[0] && A15 && !IS && !A14);

FDCPE FDCPE_EA19 (EA[19],D[4].PIN,EA_C[19],! CPLD_RESET,1'b0,EA_CE[19]);
assign EA_C[19] = !((!RW && !IOSTRB));
assign EA_CE[19] = (!A[2] && !A[1] && !A[0] && A15 && !IS && !A14);




assign FIFOADR0 = A[0];


assign FIFOADR1 = A[1];


assign FLASH_CE = !((!EA[19] && !DS));


assign FLASH_RD = !((RW && !MSTRB));


assign FLASH_WE = !((!RW && !MSTRB));


assign IDE0_CS0 = !((!ide_num && !A15 && !IS && !A14));


assign IDE0_CS1 = !((!ide_num && !A15 && !IS && A14));


assign IDE1_CS0 = !((ide_num && !A15 && !IS && !A14));


assign IDE1_CS1 = !((ide_num && !A15 && !IS && A14));


assign IDE_A[0] = A[0];


assign IDE_A[1] = A[1];


assign IDE_A[2] = A[2];


assign IDE_A[3] = A[3];