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📄 my.rpt

📁 TMS3205402Verilog HDL源码
💻 RPT
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  5: A<2>              11: D<1>.PIN          16: ide_num 
  6: CARD0<2>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
IDE_A<2>             ....X................................... 1
IDE0_CS1             XX...........X.X........................ 4
IDE1_CS1             XX...........X.X........................ 4
IDE1_CS0             XX...........X.X........................ 4
IDE0_CS0             XX...........X.X........................ 4
CARD0_RST            XXXXX..X...XXXX......................... 10
CARD0_CLK            .....X..X............................... 2
CARD0_LED            XXXXX..X..X.XXX......................... 10
CARD0_DATA           XXXXX.XX.X..XXX......................... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
D<15>                 2       0     0   3     FB3_1   39    I/O     I/O
LED0                  3       0     0   2     FB3_2   32    GCK/I/O O
D<13>                 3       0     0   2     FB3_3   41    I/O     I/O
D<11>                 3       0     0   2     FB3_4   44    I/O     I/O
(unused)              0       0     0   5     FB3_5   33    I/O     I
(unused)              0       0     0   5     FB3_6   34    I/O     I
D<9>                  3       0     0   2     FB3_7   46    I/O     I/O
(unused)              0       0     0   5     FB3_8   38    GCK/I/O GCK
D<14>                 3       0     0   2     FB3_9   40    I/O     I/O
D<8>                  3       0     0   2     FB3_10  48    I/O     I/O
D<12>                 3       0     0   2     FB3_11  43    I/O     I/O
D<10>                 3       0     0   2     FB3_12  45    I/O     I/O
(unused)              0       0     0   5     FB3_13        (b)     
D<7>                  4       0     0   1     FB3_14  49    I/O     I/O
D<6>                  4       0     0   1     FB3_15  50    I/O     I/O
(unused)              0       0     0   5     FB3_16        (b)     
D<5>                  4       0     0   1     FB3_17  51    I/O     I/O
(unused)              0       0     0   5     FB3_18        (b)     

Signals Used by Logic in Function Block
  1: A14               10: IS                18: IDE_D<9>.PIN 
  2: A15               11: PB<5>.PIN         19: IDE_D<10>.PIN 
  3: A<0>              12: PB<6>.PIN         20: IDE_D<11>.PIN 
  4: A<1>              13: PB<7>.PIN         21: IDE_D<12>.PIN 
  5: A<2>              14: IDE_D<5>.PIN      22: IDE_D<13>.PIN 
  6: A<3>              15: IDE_D<6>.PIN      23: IDE_D<14>.PIN 
  7: A<4>              16: IDE_D<7>.PIN      24: IDE_D<15>.PIN 
  8: D<0>.PIN          17: IDE_D<8>.PIN      25: RW 
  9: IOSTRB           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<15>                .X......XX.............XX............... 5
LED0                 XXXXX..XXX..............X............... 9
D<13>                XXXXXXX.XX...........X..X............... 11
D<11>                XXXXXXX.XX.........X....X............... 11
D<9>                 XXXXXXX.XX.......X......X............... 11
D<14>                XXXXXXX.XX............X.X............... 11
D<8>                 XXXXXXX.XX......X.......X............... 11
D<12>                XXXXXXX.XX..........X...X............... 11
D<10>                XXXXXXX.XX........X.....X............... 11
D<7>                 XXXXXXX.XX..X..X........X............... 12
D<6>                 XXXXXXX.XX.X..X.........X............... 12
D<5>                 XXXXXXX.XXX..X..........X............... 12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
IDE_D<10>             2       0     0   3     FB4_1   118   I/O     I/O
IDE_D<13>             2       0     0   3     FB4_2   126   I/O     I/O
IDE_A<3>              1       0     0   4     FB4_3   133   I/O     O
(unused)              0       0     0   5     FB4_4         (b)     
IDE_D<2>              2       0     0   3     FB4_5   128   I/O     I/O
IDE_D<14>             2       0     0   3     FB4_6   129   I/O     I/O
(unused)              0       0     0   5     FB4_7         (b)     
IDE_D<1>              2       0     0   3     FB4_8   130   I/O     I/O
IDE_D<15>             2       0     0   3     FB4_9   131   I/O     I/O
IDE_RD                1       0     0   4     FB4_10  135   I/O     O
IDE_D<0>              2       0     0   3     FB4_11  132   I/O     I/O
IDE_WR                1       0     0   4     FB4_12  134   I/O     O
(unused)              0       0     0   5     FB4_13  137   I/O     
(unused)              0       0     0   5     FB4_14  136   I/O     I
INT3                  1       0     0   4     FB4_15  138   I/O     O
LED1                  1       0     0   4     FB4_16  139   I/O     O
IDE_A<1>              1       0     0   4     FB4_17  140   I/O     O
COUNT<2>              1       0     0   4     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: A15                7: D<10>.PIN         13: PA3 
  2: A<1>               8: D<13>.PIN         14: IOSTRB 
  3: A<3>               9: D<14>.PIN         15: IS 
  4: COUNT<0>          10: D<15>.PIN         16: PA7 
  5: COUNT<1>          11: D<1>.PIN          17: RW 
  6: D<0>.PIN          12: D<2>.PIN         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
IDE_D<10>            X.....X......XX.X....................... 5
IDE_D<13>            X......X.....XX.X....................... 5
IDE_A<3>             ..X..................................... 1
IDE_D<2>             X..........X.XX.X....................... 5
IDE_D<14>            X.......X....XX.X....................... 5
IDE_D<1>             X.........X..XX.X....................... 5
IDE_D<15>            X........X...XX.X....................... 5
IDE_RD               X............XX.X....................... 4
IDE_D<0>             X....X.......XX.X....................... 5
IDE_WR               X............XX.X....................... 4
INT3                 ............X........................... 1
LED1                 ...............X........................ 1
IDE_A<1>             .X...................................... 1
COUNT<2>             ...XX................................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               37/17
Number of signals used by logic mapping into function block:  37
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
D<4>                  5       0     0   0     FB5_2   52    I/O     I/O
(unused)              0       0     0   5     FB5_3   59    I/O     I
(unused)              0       0     0   5     FB5_4         (b)     
D<3>                  5       0     0   0     FB5_5   53    I/O     I/O
D<2>                  5       0     0   0     FB5_6   54    I/O     I/O
(unused)              0       0   \/4   1     FB5_7   66    I/O     (b)
D<1>                  9       4<-   0   0     FB5_8   56    I/O     I/O
D<0>                  9       4<-   0   0     FB5_9   57    I/O     I/O
DRAM_CE               1       0   /\4   0     FB5_10  68    I/O     O
(unused)              0       0     0   5     FB5_11  58    I/O     I
FLASH_RD              1       0     0   4     FB5_12  60    I/O     O
PRAM_CE               1       0     0   4     FB5_13  70    I/O     O
FLASH_CE              1       0     0   4     FB5_14  61    I/O     O
FLASH_WE              1       0     0   4     FB5_15  64    I/O     O
(unused)              0       0     0   5     FB5_16        (b)     
PRAM_WE               1       0     0   4     FB5_17  69    I/O     O
(unused)              0       0     0   5     FB5_18        (b)     

Signals Used by Logic in Function Block
  1: A14               14: EA<17>            26: IDE_D<4>.PIN 
  2: A15               15: EA<18>            27: CARD0_DATA.PIN 
  3: A<0>              16: EA<19>            28: CARD1_DATA.PIN 
  4: A<1>              17: FLAGB             29: PB<0>.PIN 
  5: A<2>              18: FLAGC             30: PB<1>.PIN 
  6: A<3>              19: IOSTRB            31: PB<2>.PIN 
  7: A<4>              20: IS                32: PB<3>.PIN 
  8: CARD0_FLG         21: MSTRB             33: PB<4>.PIN 
  9: CARD1_FLG         22: IDE_D<0>.PIN      34: PA0 
 10: CARD_NUM          23: IDE_D<1>.PIN      35: PA1 
 11: DS                24: IDE_D<2>.PIN      36: PS 
 12: EA<15>            25: IDE_D<3>.PIN      37: RW 
 13: EA<16>           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<4>                 XXXXXXX........X..XX.....X......X...X... 13
D<3>                 XXXXXXX.......X...XX....X......X....X... 13
D<2>                 XXXXXXX......X....XX...X......X.....X... 13
D<1>                 XXXXXXXXXX..X....XXX..X......X....X.X... 18
D<0>                 XXXXXXX..X.X....X.XX.X....XXX....X..X... 18
DRAM_CE              ..........X....X........................ 2
FLASH_RD             ....................X...............X... 2
PRAM_CE              ...................................X.... 1
FLASH_CE             ..........X....X........................ 2
FLASH_WE             ....................X...............X... 2
PRAM_WE              ....................X...............X... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
PB<1>                 2       0     0   3     FB6_2   106   I/O     I/O
(unused)              0       0     0   5     FB6_3         (b)     
(unused)              0       0     0   5     FB6_4   111   I/O     
(unused)              0       0     0   5     FB6_5   110   I/O     
(unused)              0       0     0   5     FB6_6   112   I/O     
(unused)              0       0     0   5     FB6_7         (b)     
IDE_D<8>              2       0     0   3     FB6_8   113   I/O     I/O
IDE_D<9>              2       0     0   3     FB6_9   116   I/O     I/O
IDE_D<7>              2       0     0   3     FB6_10  115   I/O     I/O
IDE_D<5>              2       0     0   3     FB6_11  119   I/O     I/O
IDE_D<11>             2       0     0   3     FB6_12  120   I/O     I/O
(unused)              0       0     0   5     FB6_13        (b)     
IDE_D<4>              2       0     0   3     FB6_14  121   I/O     I/O
IDE_D<12>             2       0     0   3     FB6_15  124   I/O     I/O
IDE_D<6>              2       0     0   3     FB6_16  117   I/O     I/O
IDE_D<3>              2       0     0   3     FB6_17  125   I/O     I/O
COUNT<0>              0       0     0   5     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: A14                7: D<1>.PIN          13: D<9>.PIN 
  2: A15                8: D<3>.PIN          14: IOSTRB 
  3: A<2>               9: D<4>.PIN          15: IS 
  4: A<3>              10: D<5>.PIN          16: D<7>.PIN 
  5: D<11>.PIN         11: D<6>.PIN          17: RW 
  6: D<12>.PIN         12: D<8>.PIN         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
PB<1>                XXXX..X......XX.X....................... 8
IDE_D<8>             .X.........X.XX.X....................... 5
IDE_D<9>             .X..........XXX.X....................... 5
IDE_D<7>             .X...........XXXX....................... 5
IDE_D<5>             .X.......X...XX.X....................... 5
IDE_D<11>            .X..X........XX.X....................... 5
IDE_D<4>             .X......X....XX.X....................... 5
IDE_D<12>            .X...X.......XX.X....................... 5
IDE_D<6>             .X........X..XX.X....................... 5
IDE_D<3>             .X.....X.....XX.X....................... 5
COUNT<0>             ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB7_1         (b)     
PRAM_RD               1       0     0   4     FB7_2   71    I/O     O
SLRD                  1       0     0   4     FB7_3   75    I/O     O
(unused)              0       0     0   5     FB7_4         (b)     
SLWR                  1       0     0   4     FB7_5   74    I/O     O
EA<19>                3       0     0   2     FB7_6   76    I/O     O
(unused)              0       0     0   5     FB7_7   77    I/O     
(unused)              0       0     0   5     FB7_8   78    I/O     
DRAM_RD2              1       0     0   4     FB7_9   80    I/O     O
(unused)              0       0     0   5     FB7_10  79    I/O     
(unused)              0       0     0   5     FB7_11  82    I/O     
DRAM_WE3              1       0     0   4     FB7_12  85    I/O     O
(unused)              0       0     0   5     FB7_13  81    I/O     
(unused)              0       0     0   5     FB7_14  86    I/O     I
PKTEND                0       0     0   5     FB7_15  87    I/O     O
(unused)              0       0     0   5     FB7_16  83    I/O     
FIFOADR1              1       0     0   4     FB7_17  88    I/O     O
COUNT<3>              1       0     0   4     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: A14                6: A<3>              11: IOSTRB 
  2: A15                7: COUNT<0>          12: IS 
  3: A<0>               8: COUNT<1>          13: MSTRB 
  4: A<1>               9: COUNT<2>          14: RW 
  5: A<2>              10: D<4>.PIN         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
PRAM_RD              ............XX.......................... 2
SLRD                 XX..XX....XX.X.......................... 7
SLWR                 XX..XX....XX.X.......................... 7
EA<19>               XXXXX....XXX.X.......................... 9
DRAM_RD2             ............XX.......................... 2
DRAM_WE3             ............XX.......................... 2
PKTEND               ........................................ 0
FIFOADR1             ...X.................................... 1
COUNT<3>             ......XXX............................... 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               15/39
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
FIFOADR0              1       0     0   4     FB8_2   91    I/O     O
(unused)              0       0     0   5     FB8_3   95    I/O     I
(unused)              0       0     0   5     FB8_4   97    I/O     I
(unused)              0       0     0   5     FB8_5   92    I/O     I
SLOE                  1       0     0   4     FB8_6   93    I/O     O
(unused)              0       0     0   5     FB8_7         (b)     
(unused)              0       0     0   5     FB8_8   94    I/O     I
(unused)              0       0     0   5     FB8_9   96    I/O     I
PB<6>                 2       0     0   3     FB8_10  101   I/O     I/O
(unused)              0       0     0   5     FB8_11  98    I/O     
PB<7>                 2       0     0   3     FB8_12  100   I/O     I/O
PB<4>                 2       0     0   3     FB8_13  103   I/O     I/O
PB<5>                 2       0     0   3     FB8_14  102   I/O     I/O
PB<3>                 2       0     0   3     FB8_15  104   I/O     I/O
PB<0>                 2       0     0   3     FB8_16  107   I/O     I/O

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