📄 my.rpt
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cpldfit: version H.38 Xilinx Inc.
Fitter Report
Design Name: my Date: 10-25-2007, 10:54PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
89 /144 ( 62%) 197 /720 ( 27%) 158/432 ( 37%) 20 /144 ( 14%) 103/117 ( 88%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 14/18 17/54 37/90 9/15
FB2 9/18 16/54 16/90 9/15
FB3 12/18 25/54 38/90 12/15
FB4 14/18 17/54 21/90 13/15
FB5 11/18 37/54 39/90 11/14
FB6 11/18 17/54 20/90 10/13
FB7 9/18 14/54 10/90 8/15
FB8 9/18 15/54 16/90 9/15
----- ----- ----- -----
89/144 158/432 197/720 81/117
* - Resource is exhausted
** Global Control Resources **
Signal 'GCLK' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'CPLD_RESET' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 21 21 | I/O : 96 109
Output : 39 39 | GCK/IO : 3 3
Bidirectional : 42 42 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 104 104
** Power Data **
There are 89 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 81 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
CARD1_DATA 4 11 FB1_1 23 I/O I/O STD FAST RESET
EA<17> 3 9 FB1_5 19 I/O O STD FAST RESET
EA<18> 3 9 FB1_6 20 I/O O STD FAST RESET
EA<16> 3 9 FB1_8 21 I/O O STD FAST RESET
EA<15> 3 9 FB1_9 22 I/O O STD FAST RESET
CARD1_LED 3 10 FB1_11 24 I/O O STD FAST RESET
CARD1_CLK 1 2 FB1_12 26 I/O O STD FAST
CARD1_RST 3 10 FB1_14 27 I/O O STD FAST RESET
IDE_A<0> 1 1 FB1_17 30 GCK/I/O O STD FAST
IDE_A<2> 1 1 FB2_1 142 I/O O STD FAST
IDE0_CS1 1 4 FB2_4 4 I/O O STD FAST
IDE1_CS1 1 4 FB2_5 2 GTS/I/O O STD FAST
IDE1_CS0 1 4 FB2_6 3 GTS/I/O O STD FAST
IDE0_CS0 1 4 FB2_8 5 GTS/I/O O STD FAST
CARD0_RST 3 10 FB2_9 6 GTS/I/O O STD FAST RESET
CARD0_CLK 1 2 FB2_10 7 I/O O STD FAST
CARD0_LED 3 10 FB2_12 10 I/O O STD FAST RESET
CARD0_DATA 4 11 FB2_14 11 I/O I/O STD FAST RESET
D<15> 2 5 FB3_1 39 I/O I/O STD FAST
LED0 3 9 FB3_2 32 GCK/I/O O STD FAST RESET
D<13> 3 11 FB3_3 41 I/O I/O STD FAST
D<11> 3 11 FB3_4 44 I/O I/O STD FAST
D<9> 3 11 FB3_7 46 I/O I/O STD FAST
D<14> 3 11 FB3_9 40 I/O I/O STD FAST
D<8> 3 11 FB3_10 48 I/O I/O STD FAST
D<12> 3 11 FB3_11 43 I/O I/O STD FAST
D<10> 3 11 FB3_12 45 I/O I/O STD FAST
D<7> 4 12 FB3_14 49 I/O I/O STD FAST
D<6> 4 12 FB3_15 50 I/O I/O STD FAST
D<5> 4 12 FB3_17 51 I/O I/O STD FAST
IDE_D<10> 2 5 FB4_1 118 I/O I/O STD FAST
IDE_D<13> 2 5 FB4_2 126 I/O I/O STD FAST
IDE_A<3> 1 1 FB4_3 133 I/O O STD FAST
IDE_D<2> 2 5 FB4_5 128 I/O I/O STD FAST
IDE_D<14> 2 5 FB4_6 129 I/O I/O STD FAST
IDE_D<1> 2 5 FB4_8 130 I/O I/O STD FAST
IDE_D<15> 2 5 FB4_9 131 I/O I/O STD FAST
IDE_RD 1 4 FB4_10 135 I/O O STD FAST
IDE_D<0> 2 5 FB4_11 132 I/O I/O STD FAST
IDE_WR 1 4 FB4_12 134 I/O O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
INT3 1 1 FB4_15 138 I/O O STD FAST
LED1 1 1 FB4_16 139 I/O O STD FAST
IDE_A<1> 1 1 FB4_17 140 I/O O STD FAST
D<4> 5 13 FB5_2 52 I/O I/O STD FAST
D<3> 5 13 FB5_5 53 I/O I/O STD FAST
D<2> 5 13 FB5_6 54 I/O I/O STD FAST
D<1> 9 18 FB5_8 56 I/O I/O STD FAST
D<0> 9 18 FB5_9 57 I/O I/O STD FAST
DRAM_CE 1 2 FB5_10 68 I/O O STD FAST
FLASH_RD 1 2 FB5_12 60 I/O O STD FAST
PRAM_CE 1 1 FB5_13 70 I/O O STD FAST
FLASH_CE 1 2 FB5_14 61 I/O O STD FAST
FLASH_WE 1 2 FB5_15 64 I/O O STD FAST
PRAM_WE 1 2 FB5_17 69 I/O O STD FAST
PB<1> 2 8 FB6_2 106 I/O I/O STD FAST
IDE_D<8> 2 5 FB6_8 113 I/O I/O STD FAST
IDE_D<9> 2 5 FB6_9 116 I/O I/O STD FAST
IDE_D<7> 2 5 FB6_10 115 I/O I/O STD FAST
IDE_D<5> 2 5 FB6_11 119 I/O I/O STD FAST
IDE_D<11> 2 5 FB6_12 120 I/O I/O STD FAST
IDE_D<4> 2 5 FB6_14 121 I/O I/O STD FAST
IDE_D<12> 2 5 FB6_15 124 I/O I/O STD FAST
IDE_D<6> 2 5 FB6_16 117 I/O I/O STD FAST
IDE_D<3> 2 5 FB6_17 125 I/O I/O STD FAST
PRAM_RD 1 2 FB7_2 71 I/O O STD FAST
SLRD 1 7 FB7_3 75 I/O O STD FAST
SLWR 1 7 FB7_5 74 I/O O STD FAST
EA<19> 3 9 FB7_6 76 I/O O STD FAST RESET
DRAM_RD2 1 2 FB7_9 80 I/O O STD FAST
DRAM_WE3 1 2 FB7_12 85 I/O O STD FAST
PKTEND 0 0 FB7_15 87 I/O O STD FAST
FIFOADR1 1 1 FB7_17 88 I/O O STD FAST
FIFOADR0 1 1 FB8_2 91 I/O O STD FAST
SLOE 1 6 FB8_6 93 I/O O STD FAST
PB<6> 2 8 FB8_10 101 I/O I/O STD FAST
PB<7> 2 8 FB8_12 100 I/O I/O STD FAST
PB<4> 2 8 FB8_13 103 I/O I/O STD FAST
PB<5> 2 8 FB8_14 102 I/O I/O STD FAST
PB<3> 2 8 FB8_15 104 I/O I/O STD FAST
PB<0> 2 8 FB8_16 107 I/O I/O STD FAST
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
PB<2> 2 8 FB8_17 105 I/O I/O STD FAST
** 8 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
COUNT<1> 1 1 FB1_10 STD RESET
ide_num 3 9 FB1_13 STD RESET
CARD_NUM 3 9 FB1_15 STD RESET
CARD1<2> 3 10 FB1_16 STD RESET
CARD0<2> 3 10 FB1_18 STD RESET
COUNT<2> 1 2 FB4_18 STD RESET
COUNT<0> 0 0 FB6_18 STD RESET
COUNT<3> 1 3 FB7_18 STD RESET
** 23 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
DS FB1_2 16 I/O I
PS FB1_3 17 I/O I
CARD1_FLG FB1_4 25 I/O I
A<3> FB1_10 31 I/O I
A<0> FB1_16 35 I/O I
CPLD_RESET FB2_2 143 GSR/I/O GSR
CARD0_FLG FB2_11 9 I/O I
IOSTRB FB2_13 12 I/O I
MSTRB FB2_15 13 I/O I
RW FB2_16 14 I/O I
IS FB2_17 15 I/O I
A<2> FB3_5 33 I/O I
A<1> FB3_6 34 I/O I
GCLK FB3_8 38 GCK/I/O GCK
A<4> FB4_14 136 I/O I
A15 FB5_3 59 I/O I
A14 FB5_11 58 I/O I
PA7 FB7_14 86 I/O I
PA0 FB8_3 95 I/O I
FLAGB FB8_4 97 I/O I
PA3 FB8_5 92 I/O I
PA1 FB8_8 94 I/O I
FLAGC FB8_9 96 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 17/37
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
CARD1_DATA 4 0 0 1 FB1_1 23 I/O I/O
(unused) 0 0 0 5 FB1_2 16 I/O I
(unused) 0 0 0 5 FB1_3 17 I/O I
(unused) 0 0 0 5 FB1_4 25 I/O I
EA<17> 3 0 0 2 FB1_5 19 I/O O
EA<18> 3 0 0 2 FB1_6 20 I/O O
(unused) 0 0 0 5 FB1_7 (b)
EA<16> 3 0 0 2 FB1_8 21 I/O O
EA<15> 3 0 0 2 FB1_9 22 I/O O
COUNT<1> 1 0 0 4 FB1_10 31 I/O I
CARD1_LED 3 0 0 2 FB1_11 24 I/O O
CARD1_CLK 1 0 0 4 FB1_12 26 I/O O
ide_num 3 0 0 2 FB1_13 (b) (b)
CARD1_RST 3 0 0 2 FB1_14 27 I/O O
CARD_NUM 3 0 0 2 FB1_15 28 I/O (b)
CARD1<2> 3 0 0 2 FB1_16 35 I/O I
IDE_A<0> 1 0 0 4 FB1_17 30 GCK/I/O O
CARD0<2> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: A14 7: CARD1_DATA 13: D<2>.PIN
2: A15 8: CARD_NUM 14: D<3>.PIN
3: A<0> 9: COUNT<0> 15: IOSTRB
4: A<1> 10: COUNT<3> 16: IS
5: A<2> 11: D<0>.PIN 17: RW
6: CARD1<2> 12: D<1>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CARD1_DATA XXXXX.XX..X...XXX....................... 11
EA<17> XXXXX.......X.XXX....................... 9
EA<18> XXXXX........XXXX....................... 9
EA<16> XXXXX......X..XXX....................... 9
EA<15> XXXXX.....X...XXX....................... 9
COUNT<1> ........X............................... 1
CARD1_LED XXXXX..X...X..XXX....................... 10
CARD1_CLK .....X...X.............................. 2
ide_num XXXXX.....X...XXX....................... 9
CARD1_RST XXXXX..X.....XXXX....................... 10
CARD_NUM XXXXX.....X...XXX....................... 9
CARD1<2> XXXXX..X....X.XXX....................... 10
IDE_A<0> ..X..................................... 1
CARD0<2> XXXXX..X....X.XXX....................... 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
IDE_A<2> 1 0 0 4 FB2_1 142 I/O O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O GSR
(unused) 0 0 0 5 FB2_3 (b)
IDE0_CS1 1 0 0 4 FB2_4 4 I/O O
IDE1_CS1 1 0 0 4 FB2_5 2 GTS/I/O O
IDE1_CS0 1 0 0 4 FB2_6 3 GTS/I/O O
(unused) 0 0 0 5 FB2_7 (b)
IDE0_CS0 1 0 0 4 FB2_8 5 GTS/I/O O
CARD0_RST 3 0 0 2 FB2_9 6 GTS/I/O O
CARD0_CLK 1 0 0 4 FB2_10 7 I/O O
(unused) 0 0 0 5 FB2_11 9 I/O I
CARD0_LED 3 0 0 2 FB2_12 10 I/O O
(unused) 0 0 0 5 FB2_13 12 I/O I
CARD0_DATA 4 0 0 1 FB2_14 11 I/O I/O
(unused) 0 0 0 5 FB2_15 13 I/O I
(unused) 0 0 0 5 FB2_16 14 I/O I
(unused) 0 0 0 5 FB2_17 15 I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: A14 7: CARD0_DATA 12: D<3>.PIN
2: A15 8: CARD_NUM 13: IOSTRB
3: A<0> 9: COUNT<3> 14: IS
4: A<1> 10: D<0>.PIN 15: RW
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