top.v.txt

TMS3205402Verilog HDL源码

module top(
	// DSP
	CPLD_RESET,

	MSTRB,
	IOSTRB,
	RW,

	DS,
	PS,
	IS,

	EA,
	A,
	A14,
	A15,
	D,

	INT3,

	FLASH_CE,
	FLASH_RD,
	FLASH_WE,
	DRAM_CE,
	DRAM_RD,
	DRAM_WE,
	PRAM_CE,
	PRAM_RD,
	PRAM_WE,
	
	// IDE
	IDE0_CS0,
	IDE0_CS1,
	IDE1_CS0,
	IDE1_CS1,
	IDE_A,
	IDE_D,
	IDE_RD,
	IDE_WR,
//	IDE_RDY,
	LED,
	
	// USB
	PA0,
	PA1,
	SLOE,
	PA3,
	FIFOADR0,
	FIFOADR1,
	PKTEND,
	PA7,
	PB,
	PD,
	SLRD,
	SLWR,
	FLAGA,
	FLAGB,
	FLAGC,
	IFCLK);
	
	input	CPLD_RESET;
	input	MSTRB;
	input	IOSTRB;
	input	RW;
	input	DS;
	input	PS;
	input	IS;
	output	[19:15]	EA;
	input	[4:0]	A;
	input	A14;
	input	A15;
	inout	[15:0]	D;
	output	INT3;
	output	FLASH_CE;
	output	FLASH_RD;
	output	FLASH_WE;
	output	DRAM_CE;
	output	DRAM_RD;
	output	DRAM_WE;
	output	PRAM_CE;
	output	PRAM_RD;
	output	PRAM_WE;

	output	IDE0_CS0;
	output	IDE0_CS1;
	output	IDE1_CS0;
	output	IDE1_CS1;
	output	[3:0] IDE_A;
	inout	[15:0] IDE_D;
	output	IDE_RD;
	output	IDE_WR;
	output	[1:0] LED;
	
	
	input	PA0;
	input	PA1;
	output	SLOE;
	input	PA3;
	output	FIFOADR0;
	output	FIFOADR1;
	output	PKTEND;
	input	PA7;
	
	inout	[7:0] PB;
	inout	[7:0] PD;
	output	SLRD;
	output	SLWR;
	input	FLAGA;	// Programmable
	input	FLAGB;	// Full
	input	FLAGC;	// Empty
	input	IFCLK;
	
	// DSP
	assign DRAM_CE = DS | (!EA[19]) ;
	assign DRAM_RD = MSTRB | (!RW) ;
	assign DRAM_WE = MSTRB | RW ;
	
	assign FLASH_CE = DS | EA[19]  ;
	assign FLASH_RD = DRAM_RD ;
	assign FLASH_WE = DRAM_WE ;
	
	assign PRAM_CE = PS ;
	assign PRAM_RD = DRAM_RD ;
	assign PRAM_WE = DRAM_WE ;
	
	reg [15:0] DO;
	wire iord, iowr;
	
	assign iord = IOSTRB | (!RW) ;
	assign iowr = IOSTRB | RW ;


	wire ide_cs0,ide_cs1,reg_cs,usb_cs	;
	assign ide_cs0 = IS | A15 | A14;
	assign ide_cs1 = IS | A15 | (!A14);
	assign reg_cs = IS | (!A15) | (A14);
	assign usb_cs = IS | (!A15) | (!A14);

	wire reg_adder_cs,reg_ide_cs,reg_led_cs;
	assign reg_adder_cs = reg_cs | A[1] | A[0];
	assign reg_ide_cs = reg_cs | A[1] |(!A[0]);
	assign reg_led_cs = reg_cs | (!A[1]) | (A[0]);

//EX_ADDER	
	reg	[19:15]	EA;
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				EA[19:15] = 5'b10000 ;
			else if ( !(reg_adder_cs) )
				EA[19:15] = D[4:0] ;
				
		end
 //LED
	reg [1:0] LED;
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				LED[1:0] = 2'b10 ;
			else if ( !(reg_led_cs) )
				LED[1:0] = D[1:0] ;
		end

// IDE
 	reg ide_num;
	always @(posedge iowr or negedge CPLD_RESET)
		begin
			if (CPLD_RESET == 0) 
				ide_num = 1'b0 ;
			else if ( !(reg_ide_cs) )
				ide_num = D[0] ;
		end
	assign	IDE0_CS0 = ide_num    | ide_cs0;
	assign	IDE0_CS1 = ide_num    | ide_cs1;
	assign	IDE1_CS0 = (!ide_num) | ide_cs0;
	assign	IDE1_CS1 = (!ide_num) | ide_cs1;
	
	wire	IDE_CS;
	assign	IDE_CS = ide_cs0 & ide_cs1;
	
	assign	IDE_RD = (IDE_CS) ? 1 : iord;
	assign	IDE_WR = (IDE_CS) ? 1 : iowr;
	
	assign	IDE_A = A[3:0];
	assign	IDE_D = (IDE_CS | iowr) ? 16'bz : D;
	
	// USB
	assign INT3 = PA3;
	assign FIFOADR0 = A[0];
	assign FIFOADR1 = A[1];

	
	wire usb_state,usb_command,usb_data;
	assign usb_state = usb_cs | A[1] | A[0];
	assign usb_command = usb_cs | A[1] | (!A[0]);
	assign usb_data = usb_cs | (!A[1]) | A[0];
	reg SLOE, SLRD, SLWR;
	
	always @(usb_cs or iord or iowr)
		begin
			if (!usb_cs)
				begin
					SLOE = iord;
					SLRD = iord;
					SLWR = iowr;
				end
			else
				begin
					SLOE = 1;
					SLRD = 1;
					SLWR = 1;
				end
		end
					

	// Read Out
	always @(A15 or A[3:0] or IDE_D or EA or FLAGB or FLAGC or PA0 or PA1 or PB)
		begin
			if (!A15)
				DO = IDE_D;
			else if	( A[3:0] == 4'b0000 )
				DO = {12'bz, EA[18:15]};
			else if ( A[3:0] == 4'b0001 )
				DO = {14'bz, FLAGC, FLAGB};
			else if ( A[3:0] == 4'b0010 )
				DO = {14'bz, PA1, PA0};
			else if ( A[3:0] == 4'b0011 )
				DO = {8'bz, PB[7:0]};
			else
				DO = 16'bz;
		end
	
	assign	D = (iord) ? 16'bz : DO;
	
endmodule