sevenseg_case_tb.tf

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg [3:0] hex;


// Outputs
    wire [7:0] seg;


// Instantiate the UUT
    sevenseg_case uut (
        .hex(hex), 
        .seg(seg)
        );


// Initialize Inputs

initial $monitor($time, "seg = %h,  hex = %h", seg, hex);
// Initialize Inputs
initial begin
  hex = 8'h00;
end  

always
  #10 hex = hex + 8'h01;

 initial #160 $finish; //Complete simulation after 160 units

endmodule